S. Hauck. Asynchronous Design Methodologies: An Overview. Proceedings of the IEEE, 83(1):69--93, January 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....asynchronous circuits can also have significantly enhanced performance. Asynchronous design consists of handshake protocols that ensure the validity of data [9] 10] Asynchronous design methodologies, apart from DI, make timing assumptions in the protocols, function logic, or data transmission [11]. If the assumptions are invalid in the physical implementation, the circuits can glitch and fail to operate correctly. SI circuits assume indistinguishable skew on wire forks, burst mode assumes fundamental mode (the circuit will stabilize internally before new inputs arrive) and bundled data ....

S. Hauck, "Asynchronous design methodologies: An overview," Proc. IEEE, vol. 83, no. 1, pp. 69--93, Jan. 1995.

....design, asynchronous testability, domino circuits, handshake protocols, instruction length decoding, pulsed logic, relative timing, self reset logic, self timed. I. INTRODUCTION T HE OBJECTIVE of this research was to demonstrate the ability to design high speed asynchronous circuits [1] as a potential solution for microprocessor design if and when clocked design becomes too expensive. We have designed an asynchronous version of the instruction length decoder of a commercial 400 MHz clocked processor [2] For fair comparison, the prototype was implemented on the same 0.25 ....

S. Hauck, "Asynchronous design methodologies: An overview," Proc. IEEE, vol. 83, pp. 69--93, Jan. 1995.

....automated mapping from a clocked system to a self timed system from the netlist level. This allows a designer to produce the netlist using familiar design tools and HDLs with the restriction that the clocked netlist has only one global clock. Most asynchronous and self timed design methodologies [10] use custom synthesis tools and HDLs for design specification and this requires a substantial time investment on the part of the designer to learn the new methodology. A self timed design methodology known as Null Convention Logic (NCL) 11] allows the use of standard HDLs but places restrictions ....

Scott Hauck, "Asynchronous Design Methodologies: An Overview", Proceedings of the IEEE, Vol. 83, No. 1, January, 1995, pp. 69-93.

....but did not deal with the synthesis of efficient circuits using these elements. 6] and [7] have developed composition operators and algebras to model speed independence and to verify equivalence of DI specifications, respectively. 8] has developed grammars (not provably complete, see [9]) to specify DI circuits that induce a syntaxdirected translation into a basic set of primitives. 10] uses most of Keller s primitives and some more complex primitives to compile process algebras into DI circuits. 11, 12, 13, 14] have devised practical syn thesis techniques, yet they impose ....

S. Hauck, "Asynchronous design methodologies: An overview," Tech. Rep. TR 93-05-07, Department of Computer Science and Engineering, University of Washington, Seattle, 1993.

....automated mapping from a clocked system to a self timed system from the netlist level. This allows a designer to produce the netlist using familiar design tools and HDLs with the restriction that the clocked netlist has only one global clock. Most asynchronous and self timed design methodologies [10] use custom synthesis tools and HDLs for design specification and this requires a substantial time investment on the part of the designer to learn the new methodology. A self timed design methodology known as Null Convention Logic (NCL) 13] allows the use of standard HDLs (VHDL) but it places ....

Scott Hauck, "Asynchronous Design Methodologies: An Overview", Proceedings of the IEEE, Vol. 83, No. 1, January, 1995, pp. 69-93.

....(forking wires have equal delays to specific destinations) As the design of the event driven buffer is based on the delay insensitive methodology a fuller description of that timing model will be given here. For a complete description of the asynchronous design heirarchy shown in figure 1 see [18]. The fact that a delay insensitive circuit knows nothing about the delays associated with any logic element or wire raises the issue of how any such circuit can determine when a new input has been correctly received. The solution to this problem ensures that any recipient of input informs the ....

Hauck S. Asynchronous Design Methodologies: An Overview . In Proc. of the IEEE, Vol. 83, No 1, January 1995.

.... micropipeline [19] Typically, a micropipeline is composed of a hybrid of bounded delay and delay insensitive logic whose topology is to have all the processing actions, the combinatorial logic, forming a bounded delay datapath that is encapsulated within a delay insensitive control circuit [3]. The general configuration of a micropipeline employing 2 phase signalling can be seen in Figure 8 and can be translated into a top level abstract view of the ADLX pipeline, Figure 9. c c c c d(in) req1 d(out) req2 ack2 req4 req3 req1 ack4 ack1 req2 req4 req3 ack3 capture pass ....

S. Hauck. Asynchronous Design Methodologies: An Overview. Proc. of the IEEE, 83(1):69--93, January 1995.

....thesis are assumed to be pure delays. 1.2 Classes of Asynchronous Circuits Asynchronous circuits are conventionally classified based on the delay model used by them. An overview of the main approaches is provided below. For a more complete discussion, the reader is referred to the literature [43]. Delay insensitive (DI) circuits assume unbounded delays for both gates and wires; hence, they are very robust to component delay variations. The literature contains a large body of work on DI circuits [26, 77, 87, 35, 84, 13] However, it has been shown that if one uses gate libraries with only ....

....improvement in circuit complexity and performance compared to DI, SI or QDI circuits [78] However, as with fundamental mode circuits, the correct operation of these circuits depend on the validity of the delay bounds in the actual implementation. The reader is referred to the literature [61, 8, 43] for a more thorough discussion of other practical asynchronous design styles that make use of bounded delay assumptions. 1.3 Why Approximate Timing Analysis We have seen above that practical asynchronous circuits depend on certain timing con straints for their correct operation. Since ....

S. Hauck. Asynchronous design methodologies: An overview. Proceedings of the IEEE, 83(1):69-93, January 1995.

....later sections. X B P(X=1) 0.1 Z C Y C P(Y=1) 0.02 Z A P(A=1) 0.5 P(B=1) 0.2 P(C=1) 0.1 Circuit a. Circuit b. Figure 5: Reordering logic inputs. Asynchronous design One way to avoid unnecessary activity is by applying an asynchronous design methodology [6] 47][23][55] CMOS is a good technology for low power as gates mainly dissipate energy when they are switching. Normally this should correspond to the gate doing useful work, but unfortunately in a synchronous circuit this is not always the case. The circuit activity is often low (below 10 ) for one of ....

Hauck S.: "Asynchronous design methodologies: an overview", Proceedings of the IEEE, Vol. 83, No. 1, pp. 69-93, January 1995.

....with speculative execution. This design experiment is discussed in Section VI. II. Background and Related Work The theory of latency insensitive design is clearly reminiscent of many ideas which have been proposed in the asynchronous design community during the past three decades [13] [14]. In particular, the idea of a design methodology which is inherently modular is already present in the work on Macromodular Computer Systems by Clark and Molnar [15] 16] To separate the design of these modules from the design of the system and make the entire process amenable to automation, ....

Scott Hauck, "Asynchronous design methodologies: An overview," Proceedings of the IEEE, vol. 83, no. 1, Jan. 1995.

....depending on computation load. There is another recent patent on such techniques [34] Data driven techniques for DSP applications using dynamic voltage techniques has been investigated in [17] while high level voltage scheduling issues have been reported in [32] 55] Asynchronous approaches [30] are also very appropriate for circuits with continuously changing performance requirements and especially dataflow asynchronous circuits can work very well in conjunction with continuously changing supply voltages [49] 74] 8 TRANSACTIONS ON VLSI SYSTEMS Vdd Vss SLEEP SLEEP IN OUT Vdv ....

S. Hauck, "Asynchronous design methodologies: An overview," Proceedings of the IEEE, pp. 69--92, Jan. 1995.

....an example circuit. Conclusions are drawn in section 6 together with directions for further work. 2 Asynchronous Electronics Both synchronous and asynchronous digital systems assume that signals are in one of two possible states. Synchronous systems split time into discrete, regular intervals [6]. The state of the circuit is updated by the clock, with combinational logic processing values and generating the next state vector between active clock edges. As asynchronous systems do not have a global clock they cannot operate in this way. Asynchronous systems are typically classified by ....

....and generating the next state vector between active clock edges. As asynchronous systems do not have a global clock they cannot operate in this way. Asynchronous systems are typically classified by their timing model, signalling protocol and by the method used for their design and implementation [6, 7, 8]. For brevity, this paper assumes familiarity with the bounded delay and delay insensitive timing models, Muller C gates and macromodules [5, 6, 7, 8, 9, 10] 2.1 Signalling Protocols Asynchronous circuits generally use an inter element signalling scheme to act as a protocol layer for all ....

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Hauck, S. (1995), "Asynchronous design methodologies: an overview", Proceedings of the IEEE, 83(1): 69-93.

....energy consumption will be reduced without loss of performance. While power consumption savings happen whenever the switching activity is reduced, the existence of large clock distribution networks in synchronous systems diminishes the effects of switching activity reduction in logic gates alone [2]. Due to high capacitances associated with clock distributions, more than 25 of the overall dissipation of energy can be caused by the clock signals [3,4] This ratio could rise above 50 in highly pipelined circuits [5] Hence, the power reduction in synchronous systems can be realized to its ....

S. Hauck, "Asynchronous Design Methodologies: An Overview", Proceedings of IEEE, Vol. 83, No. 1, Jan. 1995, pp. 69-93.

....thesis are assumed to be pure delays. 1.2 Classes of Asynchronous Circuits Asynchronous circuits are conventionally classified based on the delay model used by them. An overview of the main approaches is provided below. For a more complete discussion, the reader is referred to the literature [43]. Delay insensitive (DI) circuits assume unbounded delays for both gates and wires; hence, they are very robust to component delay variations. The literature contains a large body of work on DI circuits [26, 77, 87, 35, 84, 13] However, it has been shown that if one uses gate libraries with only ....

....improvement in circuit complexity and performance compared to DI, SI or QDI circuits [78] However, as with fundamental mode circuits, the correct operation of these circuits depend on the validity of the delay bounds in the actual implementation. The reader is referred to the literature [61, 8, 43] for a more thorough discussion of other practical asynchronous design styles that make use of bounded delay assumptions. 1.3 Why Approximate Timing Analysis We have seen above that practical asynchronous circuits depend on certain timing constraints for their correct operation. Since component ....

S. Hauck. Asynchronous design methodologies: An overview. Proceedings of the IEEE, 83(1):69--93, January 1995.

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S. Hauck. Asynchronous Design Methodologies: An Overview. Proceedings of the IEEE, 83(1):69--93, January 1995.

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S. Hauck, "Asynchronous design methodologies: An overview," Proc. IEEE, vol. 83, pp. 69--93, 1995.

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S. Hauck. Asynchronous design methodologies: An overview. In Proc. of IEEE, volume 83, pages 69-93, 1995.

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S.Hauck, "Asynchronous Design Methodologies: An Overview", Proc. IEEE, vol.83, no.1, pp. 69-93, Jan.1995.

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Hauck, S. Asynchronous design methodologies: an overview. Proc. IEEE 83(1), Jan. 1995, 69-93.

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Scott Hauck. Asynchronous design methodologies: An overview. Proceedings of the IEEE, 83(1):69--93, January 1995.

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S. Hauck. Asynchronous design methodologies: An overview. In Proc. of IEEE, volume 83, pages 69-93, 1995.

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S. Hauck, "Asynchronous Design Methodologies: an Overview," In Proceedings of the IEEE, vol.83, no.1, pp.69-93, 1995.

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Hauck, S. Asynchronous design methodologies: An overview. Proceedings of the IEEE 83, 1 (January 1995), 69--93. 70

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S. Hauck. Asynchronous design methodologies: An overview. Proc. of the IEEE, 83(1):69--93, 1995.

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S. Hauck, "Asynchronous design methodologies: an overview", IEEE Proceedings, vol. 83, no. 1, pp. 67-93, 1995

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