U. Holtmann and R. Ernst. Combining MBP-speculative computation and loop pipelining in high-level synthesis. In European Design and Test Conference, 1995. 20  Home/Search   Document Details and Download   Summary   Related Articles   Check

....operations in a DFG from one iteration of the loop body to the next. Percolation based synthesis [13] applies the perfect pipelining approach to high level synthesis. Cathedral II [12] applies loop folding to overlap successive iterations of a loop body in a data flow graph. 5 Holtmann and Ernst [17] apply loop pipelining to designs with conditional branches. They schedule operations on the most probable path through the loop body by deferring operations on other paths. Compensation code is executed for an incorrect prediction. Yu et al. 18] extend rotation scheduling for control data flow ....

U. Holtmann and R. Ernst. Combining MBP-speculative computation and loop pipelining in high-level synthesis. In European Design and Test Conference, 1995. 20

....aware resource binding techniques [8] 8 Loop transformations can also be used in high level synthesis. Potasman et al. 41] demonstrated the improvements that can be obtained by applying the parallelizing compiler technique of perfect loop pipelining to data flow designs. Holtmann et al. [42] apply loop pipelining to the program path that has the highest predicted probability to be taken, thereby deferring operations belonging to other paths. 3 Role of Parallelizing Compiler Transformations in High Level Synthesis As mentioned in the previous section, recent high level synthesis ....

U. Holtmann and R. Ernst. Combining MBP-speculative computation and loop pipelining in high-level synthesis. In European Design and Test Conference, 1995. 54

....in [2] Code motion is captured by recent scheduling methods [1] 10] 11] Some HLS methods [7] 13] cope with conditional code. Path based Scheduling [3] optimizes execution paths as fast as possible, but speculation is not allowed. Speculation is usually addressed for speeding up execution [6] [9] Little work is reported on code motion for worst case execution. A survey of state equivalence techniques for sequential synthesis is given in [4] The criterion for pipelining detection in [1] relies on equivalence classes, yet state equivalence is not addressed. To our knowledge, no other ....

U. Holtmann and R. Ernst, "Combining MBP--Speculative Computation and Loop Pipelining in High--Level Synthesis", Proc. European Design and Test Conf., pp.550--555, 1995.

.... of a computation before it is known that the control path to which it belongs will be executed (for example, execution of the code after a branch statement before the branch condition itself is evaluated) There has been previous work on speculative execution in the areas of high level synthesis [3, 4, 5] as well as high performance compilation [6, 7, 8, 9, 10, 11] This paper presents techniques to integrate speculative execution into scheduling during high level synthesis of control flow intensive designs. In that context, we demonstrate that not using information such as resource constraints ....

....resulting in speculative execution. However, the algorithm considers acyclic CDFGs, and is hence not well suited for optimizing data dependent loops. Speculative execution was shown to have significant performance benefits in coprocessor synthesis in [3] and was combined with loop pipelining in [5]. However, the techniques presented there are based on performing speculative execution along a single path (the most probable path) only, and executing the less probable paths only after it has been confirmed that a prediction error has occurred. This is a coarse grain approach to incorporating ....

U. Holtmann and R. Ernst, "Combining MBP-speculative computation and loop pipelining in high-level synthesis," in Proc. European Design & Test Conf., pp. 550--556, Mar. 1995.

....example, execution of the code after a branch statement before the branch condition itself is evaluated) It has been used to overcome, to some extent, the scheduling bottlenecks imposed by control flow. There has been previous work on speculative execution in the areas of high level synthesis [1, 2, 3] as well as high performance compilation [4, 5] Previous work [1, 2, 3] in high level synthesis has attempted to locate single or multiple paths for speculation prior to scheduling. This paper presents techniques to integrate speculative execution into scheduling during high level synthesis of ....

....condition itself is evaluated) It has been used to overcome, to some extent, the scheduling bottlenecks imposed by control flow. There has been previous work on speculative execution in the areas of high level synthesis [1, 2, 3] as well as high performance compilation [4, 5] Previous work [1, 2, 3] in high level synthesis has attempted to locate single or multiple paths for speculation prior to scheduling. This paper presents techniques to integrate speculative execution into scheduling during high level synthesis of control flow intensive designs. In that context, we demonstrate that not ....

U. Holtmann and R. Ernst, "Combining MBP-speculative computation and loop pipelining in high-level synthesis," in Proc. European Design & Test Conf., pp. 550--556, Mar. 1995.

....this assumption can be relaxed with special hardware support, as suggested in [14] for instance. A comprehensive overview of hardware support for speculative execution can be found in [6] In particular, the use of hardware support for speculative execution in HLS is addressed, for instance, in [7]. IV. MODELING AVAILABILITY ANALYSIS In DFGs containing no conditionals, availability analysis is very simple. Essentially, an operation is available if it is not yet scheduled and all its predecessors are scheduled. However, availability analysis for DFGs containing conditionals is a more ....

U. Holtmann and R. Ernst, "Combining MBP-Speculative Computation and Loop Pipelining in HighLevel Synthesis," in Proc. European Design and Test Conference, pp. 550-555, 1995.

....all possible execution paths, schedules them independently,and combines them in a final schedule. A listscheduling method based on condition vectors is introduced in [8] A general limitation of the two algorithms is that they do not take careful scheduling decisions across basic block boundaries. [11] discusses a speculative computation based scheduling algorithm, that optimizes the high probability execution paths. If the path is predicted incorrectly, then a prediction error correction phase takes place. The correction phase overhead might become large for designs at levels of granularity ....

U. Holtmann, R. Ernst. Combining mbp-speculative computation and loop pipelining in high-level synthesis. Proceedings of the ED & TC, pages 550--556, 1995.

.... [3] To allow more aggressive scheduling or prediction across multiple paths, some static prediction approaches also depend on specialized register files [14, 2] In this paper we will present multiple path prediction (MPP) a compile time technique originally developed for high level synthesis [8]. MPP is a code transformation strategy that improves the optimization potential when software pipelining or loop pipelining [1] is applied for loop scheduling. MPP can lead to performance and or memory size improvements on the above VLIW DSPs without need for additional architectural support. MPP ....

....problem, heuristics (like the two lower bound heuristics described in section 2.1) are applied in order to determine the parameters t n;P and t i;p ; p 2 P . We won t give any details here, since a description of MPP and its effectiveness in the context of high level synthesis can be found in [8]. In the remaining parts of this paper we will describe our experiences when applying MPP on VLIW multimedia processors. Table 1: VLIW Multimedia DSPs TriMedia TMS320C60 instruction slots 5 8 branch delay slots 3 5 ALUs 5 6 multipliers 2 2 RAM ports 2 2 registers 126 32 3. MPP on VLIW ....

U. Holtmann and R. Ernst. Combining MBP-speculative computation and loop pipelining in high-level synthesis. In ED&TC, pages 550--555, 1995.

....1) consisting of a processor and a coprocessor which are synchronized with the environment by buffer memories. It is necessary to buffer the fixed rate video I O to allow for non trivial processor coprocessor design solutions. Cosyma, along with its high level synthesis (HLS) system BSS 1 [3], allowed us not only to do useful code optimization but also to efficiently prune the design space to find an 1 Braunschweig Synthesis System memory buffer controller coprocessor processor shared memory local memory buffer memory host interface i o Figure 1: System Architecture ....

U. Holtmann and R. Ernst. Combining mbp-speculative computation and loop pipelining in high-level synthesis. In ED&TC'95, pages 550--555, 1995.

....system BSS is used as back end for the hardware part. BSS was developed for designing high performance co processors while still allowing fast design space exploration. The fast heuristic scheduler uses techniques like loop pipelining and speculative computation of control dependent operations [5]. For the objective of short turnaround times (as required for fast what if analysis in COSYMA) the user must provide the clock frequency of the target co processor and the hardware modules to be used. In the target system of our project, processor and co processor use the same clock frequencies. ....

U. Holtmann and R. Ernst. Combining mbp-speculative computation and loop pipelining in high-level synthesis. In European Design & Test Conference (ED&TC '95), pages 550-- 555, Mar. 1995.

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