M. Horowitz, C.-K. K. Yang, and S. Sidiropoulos. High-speed electrical signaling: overview and limitations. In IEEE Micro, pages 12--24, January 1998.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....redesign of equalization is required if it is used. In comparison, the losses in transmission of light are very small. An optical interconnect designed for a few meters can easily be used for kilometers. To give an idea of the numbers involved, in a 12 m RG 55U cable the loss at 2 GHz is 10 dB [16], while in a 1000 m long single mode optical fiber at 42 THz carrier frequency the loss is a mere 3 dB. The propagation loss in free space is also low for optics. 1.1.2 Other advantages of optics i. Density of interconnects. Electronics can provide very high densities of interconnects at the ....

....5.1) but the delay of global interconnects with and without repeaters is continuously increasing relative to the clock period. The propagation velocity of global interconnects with repeaters is a small fraction of the velocity of light (10 20 ) and is not expected to improve significantly [7] [16] [97] For 0.25 m technology the delay of global lines is less than a clock cycle, but for future technologies the delay will be longer than a clock cycle. If the signals can be propagated at a significant fraction of the velocity of light, e.g. 0.3 c, the delay in communication will be less ....

M. Horowitz, C. Yang, and S. Sidiropoulos, "High-speed electrical signaling: overview and limitations," IEEE Micro, pp. 12--24, Jan. 1998.

....supply noise we placed inductors in series with each of the four supplies. 5.4 Results Our tests were performed in Spice using parameters from a 0.35p, 3.3 V process. All timing measurements are taken at the fifty percent point. Under typical process parameters, the average measured FO4 delay [5] is 185 ps. We tested both the speed and robustness of the design. We observed correct multiplier operation at all five process comers. Under typical process parameters the average interstage Gasp delay is 206 ps. That gives an end to end latency of 7.4 ns. We can issue at 1.11 GHz, for eight ....

M. Horowitz, C.-K. K. Yang, and S. Sidiropoulos. Highspeed electrical signaling: Overview and limitations. IEEEMicro, 18(1):12 24, Jan./Feb. 1998.

....applications. A more cost effective solution is to perform multiplexing at the input of the transmitter before the signal is buffered up. Previous input multiplexed architecture designs use static CMOS gates to perform multiplexing and buffering to drive the final output driver as shown in Fig. 4 [8], 9] However, this design style is unable to achieve signaling rate higher than because of the bandwidth limit of CMOS gates. Fig. 5 shows the maximum signaling rate versus the degree of multiplexing. The shaded area denotes the achievable bit time. The speed is initially limited by the ....

M. Horowitz, C. K. K. Yang, and S. Sidiropoulos, "High-speed electrical signaling: Overview and limitations," IEEE Micro., vol. 18, pp. 12--24, Jan.--Feb. 1998.

....within a processing module, or processing element to another close by processing element) of a processor. In order to maintain signal integrity and a very low bit error rate in the noisy environment of such communication channels new techniques and solutions are needed. See Ref[1] and [2]) The noise consists of various components and three of the most significant noise sources are cross talk, interconnect delay (causing inter symbol interference ISI) and power supply noise. Various remedies have been proposed to deal with these different kinds of noise. They include techniques ....

....establishing robust design guidelines and rules is needed. A new interconnect centric design methodology needs to be developed. 6.0 References [1] W J Dally and J W Poulton, High Performance Electrical Signaling , proc. IEEE 5th International Conference on Massively Parallel Processing, 1998 [2] M Horowitz, C K Yang and S Sidiropoulos, High Speed Electrical Signaling: Overview and Limitations , proc. IEEE Micro, 1998 [3] Y I Ismail and E B Friedman, Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits , in proc. DAC 1999. 4] W J Dally and J W ....

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M Horowitz, C K Yang and S Sidiropoulos, "High-Speed Electrical Signaling: Overview and Limitations", proc. IEEE Micro, 1998

....schemes, and buffering strategies. At an implementation level, most current SMPs use back pressure flowcontrol to throttle the address network when end point contention causes queues to fill up. With hierarchical designs, longer relative latencies, and high bandwidth source synchronous links [20], maintaining synchronous broadcast may require a global, rather than simply local, flow control mechanism. Will problems with ordered and synchronous broadcast doom SMPs We think not, because snooping protocols depend on processing coherence transactions in a total order, but they need not ....

M. Horowitz, C.-K. K. Yang, and S. Sidiropoulos. HighSpeed Electrical Signaling: Overview and Limitations. IEEE Micro, 18(1), January/February 1998.

....In order to generate a 1 Gbit s data rate in CMOS technology, it is not required to clock the internal circuitry at gigahertz speeds. Using parallel to serial and serial to parallel techniques, gigabit second bit rates can be achieved while the internal circuits operate at much slower speeds [18]. High bit rates are achieved by using multiple slower clocks, whose phases are precisely spaced by exactly a bit period. The generation of these clocks will be explained in Section 3.1 and in greater detail in Chapter 4. Section 3.2 will explain how high speed data is transmitted and received ....

....the supply voltage will cause a frequency offset on the VCO. Phase errors will accumulate until the loop can correct for them. A step on the supply rail can cause an phase error 6 times greater for a PLL than for a DLL, and may take more than 500 ns to settle compared to less than 20 ns for a DLL [18]. PLLs are often preferred over DLLs because they can perform clock multiplication. Usually, only low frequency, off chip clock references are available, and a PLL is required to produce a high speed clock for chips such as microprocessors. DLLs are only employed if the high speed clock is ....

M. Horowitz, C-K. Yang, and S. Sidiropoulos. High-speed electrical signaling: Overview and limitations. IEEE Micro, 18(1):12--24, Jan/Feb 1998.

....on the message interface. Conventional message interfaces that take tens to thousands of cycles to send a message present a bottleneck in the advent of advanced processors that are capable of generating multiple results on chip every cycle (e.g. 1, 2, 3] and high speed signaling pads [11, 12] that are able to carry that data off chip quickly. In terms of robustness, the message interface is also the weakest link in the communication system. As user programs share the resources such as message buffers, care must be taken to shield them from one another. The challenge is to minimize ....

Mark Horowitz, Chih-Kong Ken Yang, Stefanos Sidiropoulos, "High-speed Electrical Signaling: Overview and Limitations", in IEEE Micro, January/February 1998, pp.12--24.

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M. Horowitz, C.-K. K. Yang, and S. Sidiropoulos. High-speed electrical signaling: overview and limitations. In IEEE Micro, pages 12--24, January 1998.

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M. Horowitz, C.-K. K. Yang, and S. Sidiropoulos. High-speed electrical signaling: overview and limitations. In IEEE Micro, pages 12--24, January 1998.

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Mark Horowitz, Chih-Kong Ken Yang, and Stefanos Sidiropoulos. High-speed electrical signaling: Overview and limitations. IEEE Micro, 18(1):12--24, Jan./Feb. 1998.

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M. Horowitz, C.-K. K. Yang, S. Sidiropoulos. High-speed electrical signaling: overview and limitations. IEEE Micro, January 1998, pages 12-24

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M. Horowitz, C.-K. K. Yang, and S. Sidiropoulos. High-Speed Electrical Signaling: Overview and Limitations. IEEE Micro, 18(1), January/February 1998.

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M. Horowitz, C.-K. K. Yang, and S. Sidiropoulos. Highspeed electrical signaling: Overview and limitations. IEEE Micro, 18(1):12--24, Jan./Feb. 1998.

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