W. J. Dally, M.-J. E. Lee, F.-T. An, J. Poulton, and S. Tell. High performance electrical signaling. In The Fifth International Conference on Massively Parallel Processing Using Optical Interconnections, June 1998.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....not increased at the same rate as processor clock rates. it is common today to find a 1 GHz processor connected to memory through a 133MHz back side bus. Even though active research aims to improve pin bandwidth by substantially increasing the pin transfer rates into the Gigabit per second regime [9, 11, 26], the disparity between the computation capacity and off chip bandwidth will persist for the foreseeable future. For our experiments, we scale the chip pin density according to the SIA projections for signal pin density at a fixed 400tara 2 die size. We scale the pin speeds linearly with ....

W. J. Dally, M.-J. E. Lee, F.-T. An, J. Poulton, and S. Tell. High performance electrical signaling. In The Fifth International Conference on Massively Parallel Processing Using Optical Interonnections, June 1998.

....not increased at the same rate as processor clock rates. It is common today to find a 1 GHz processor connected to memory through a 133MHz back side bus. Even though active research aims to improve pin bandwidth by substantially increasing the pin transfer rates into the Gigabit per second regime [9, 11, 26], the disparity between the computation capacity and off chip bandwidth will persist for the foreseeable future. For our experiments, we scale the chip pin density according to the SIA projections for signal pin density at a fixed 400 die size. We scale the pin speeds linearly with ....

W. J. Dally, M.-J. E. Lee, F.-T. An, J. Poulton, and S. Tell. High performance electrical signaling. In The Fifth International Conference on Massively Parallel Processing Using Optical Interconnections, June 1998.

....needs (edge to edge within a processing module, or processing element to another close by processing element) of a processor. In order to maintain signal integrity and a very low bit error rate in the noisy environment of such communication channels new techniques and solutions are needed. See Ref[1] and [2] The noise consists of various components and three of the most significant noise sources are cross talk, interconnect delay (causing inter symbol interference ISI) and power supply noise. Various remedies have been proposed to deal with these different kinds of noise. They include ....

....of power supply noise is reduced through isolation. Thus more detailed analysis into architectural and circuit models is necessary, and more effort in establishing robust design guidelines and rules is needed. A new interconnect centric design methodology needs to be developed. 6. 0 References [1] W J Dally and J W Poulton, High Performance Electrical Signaling , proc. IEEE 5th International Conference on Massively Parallel Processing, 1998 [2] M Horowitz, C K Yang and S Sidiropoulos, High Speed Electrical Signaling: Overview and Limitations , proc. IEEE Micro, 1998 [3] Y I Ismail ....

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W J Dally and J W Poulton, "High Performance Electrical Signaling", proc. IEEE 5th International Conference on Massively Parallel Processing, 1998

....I O networks. For some applications, these service guarantees must be met even in the presence of equipment failure. When a network link or router fails, the performance of the network should degrade gracefully rather than fail abruptly. Recent developments in high speed electrical signaling [10] and parallel optical links [12] enable very high performance interconnection networks. These new technologies also change the design space of interconnection networks and greatly change the cost performance equation. High speed electrical links enable router chips with total pin bandwidth ....

W. Dally and J. Poulton. High performance electrical signaling. In Proc.IEEE 5th International Conference on Massively Parallel Processing Using Optical Interconnects, 1998.

....on the message interface. Conventional message interfaces that take tens to thousands of cycles to send a message present a bottleneck in the advent of advanced processors that are capable of generating multiple results on chip every cycle (e.g. 1, 2, 3] and high speed signaling pads [11, 12] that are able to carry that data off chip quickly. In terms of robustness, the message interface is also the weakest link in the communication system. As user programs share the resources such as message buffers, care must be taken to shield them from one another. The challenge is to minimize ....

William J. Dally, Ming-Ju Edward Lee, Fu-Tai An, John Poulton, Steve Tell, "High-Performance Electrical Signaling", in the Proceedings of the Fifth International Conference on Massively Parallel Processing Using Optical Interconnections, 1998.

No context found.

W. J. Dally, M.-J. E. Lee, F.-T. An, J. Poulton, and S. Tell. High performance electrical signaling. In The Fifth International Conference on Massively Parallel Processing Using Optical Interconnections, June 1998.

No context found.

W. J. Dally, M.-J. E. Lee, F.-T. An, J. Poulton, and S. Tell. High performance electrical signaling. In The Fifth International Conference on Massively Parallel Processing Using Optical Interconnections, June 1998.

No context found.

W.J. Dally, M.-J. E. Lee, F.-T. R. An, J. Poulton, and S. Tell. High Performance Electrical Signaling. MPPOI98, 1998.

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