M. Lin, R. Tsang, D. H. C. Du, A. E. Klietz, and S. Saroff, "Performance Evaluation of the CM-5 Interconnection Network," Technical Report AHPCRC Preprint 92-111, University of Minnesota AHPCRC, October 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....property that the overall communication bandwidth remains constant at each level. Other references to fat trees include [5] 6] Unfortunately, not much is known on the communication performance of the fat trees. Most of the literature deals with the CM 5 and focuses on raw network performance [7] [8] [9] Thanks to their simplicity and expandability, lowdimensional cubes have been adopted as interconnection networks by many massively parallel machines. In the Stanford Dash there are two distinct cubes that support the cache coherence mechanisms [10] one is dedicated to the requests and the ....

M. Lin, R. Tsang, D. H. C. Du, A. E. Klietz, and S. Saroff, "Performance Evaluation of the CM-5 Interconnection Network," Tech. Rep. AHPCRC Preprint 92-111, University of Minnesota AHPCRC, October 1992.

....processors to route the message in the ascending and descending phases. Other references to fat trees include [30] 31] Unfortunately, not much is known on the communication performance of the fat trees. Most of the literature deals with the CM 5 and focuses on raw network performance [32] [33] [34] Typical communication patterns include simple sends and ping pong between pairs of nodes. Block permutations of data and grid shifts have been shown to have little or no contention on the CM 5. This makes the data network very efficient for regular communication patterns commonly used in ....

M. Lin, R. Tsang, D. H. C. Du, A. E. Klietz, and S. Saroff, "Performance Evaluation of the CM-5 Interconnection Network," Tech. Rep. AHPCRC Preprint 92-111, University of Minnesota AHPCRC, October 1992.

....system as a pool of processors and is not involved with process placement. The operating system, during initial process placement and during migration, favors placing a process within the level 1 or level 2 cluster depending on size. Consider the Fat Tree [2] the basis of Thinking Machines CM 5 [3, 4]. This is a metal interconnected hierarchical network with VLSI routing elements at each internal node. A typical problem with tree type networks is congestion near the root. When traffic exhibits a strong degree of locality, the communication is contained within the hierarchy and root congestion ....

M. Lin, R. Tsang, D. Du, A. Klietz, and S. Saroff, "Performance evaluation of the CM-5 interconnection network," Tech. Rep. AHPCRC Preprint 92-111, University of Minnesota, Army High Performance Computing Research Center, Oct. 1992.

....number of links connecting a node to its parent increases as the level increases to provide increased communication bandwidth. The rate of growth is influenced by the desired scalability and cost performance ratio. A variation of the Fat Tree network has been employed in Thinking Machine s CM 5 [2, 3]. This paper introduces an optical based approach, denoted as the space wavelength hierarchical architecture (SWHA) that achieves the Fat Tree objectives while also obtaining significant improvement in flexibility, performance and fault tolerance through wavelength division multiple access 1 ....

....on the way couplers are fabricated. The CM 5 employs a hierarchical network with increased capacity at higher hierarchical levels. The network is based on the Fat Tree [1] but differs in being a quad tree (rather than a binary tree) and in the rate of channel capacity increase at higher levels [3]. The CM 5 interconnection scheme is denoted as hypertree in [3] not the same hypertree introduced in [30] The CM 5 hypertree employs data routers at the internal nodes and processors at the leaves of the tree as in the Fat Tree. However, the CM 5 hypertree data routers provide multiple paths ....

[Article contains additional citation context not shown here]

M. Lin, R. Tsang, D. Du, A. Klietz, and S. Saroff, "Performance evaluation of the CM-5 interconnection network," Tech. Rep. AHPCRC Preprint 92-111, University of Minnesota, Army High Performance Computing Research Center, Oct. 1992.

....the applications at the inner loop level. Nonetheless, most existing machines, burdened by communication overhead that ranges from many tens to many thousands of processor cycles, are too inefficient to take advantage of parallelism at this level. The few that are lean and mean , such as [9, 10], lack robustness and lose their efficiency when software layers are used as a workaround. To effectively exploit fine grain parallelism, an efficient and robust communication architecture is necessary. 1.2 Approach This thesis focuses on the message interface. Conventional message interfaces ....

.... Figure 2 1: Past and Present Multicomputers System Processors Round Trip Remarks Features Issues iPSC 2 20 Mhz 710 S[19] 85 sofware overhead 80386 100 byte message (18 from context switches) 110 S[19] with MPC 100 byte message (Communication Co Processor) CM 5 32 Mhz SPARC 143 S swap[9] CMMD library 3.4 S swap[9] CMNF library J Machine 12.5 Mhz MDP 43 cyc[10] Streaming Injection 1024 max round trip null RPC CS 2 40 Mhz 20 S[39] Channel SPARC 24.6 S[23] DMA w active message Hardware Table Lookup 174 S[21] PARMACS macros ping pong 206 S[20] mpsc library mesg exhange T3D 150 Mhz ....

[Article contains additional citation context not shown here]

Mengjou Lin, Rose Tsang, David H. C, Du, Alan E. Klietz, Stephen Saroff, "Performance Evaluation of the CM-5 Interconnection Network", in COMPCON 1993, pp. 189--197.

No context found.

M. Lin, R. Tsang, D. H. C. Du, A. E. Klietz, and S. Saroff, "Performance Evaluation of the CM-5 Interconnection Network," Technical Report AHPCRC Preprint 92-111, University of Minnesota AHPCRC, October 1992.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC