James E. Smith and Andrew R. Pleszkun. Implementing precise interrupts in pipelined processors. IEEE Transactions on Computers, 37(5):562--573, May 1988.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... This optimization can reduce significantly the pressure on vector registers, if a sufficient number of the vector instructions executed can never to generate faults (e.g. vector shift) We can implement in order commit without modifying the clusters by adding a history buffer in the issue logic [23]. The history buffer keeps track of the changes to the renaming table and the per cluster state for each instruction in case we need to undo them. We insert and extract instructions from the history buffer in issue order. If the instruction at the buffer head completes without exception, we ....

J. Smith and A. Pleszkun. Implementing Precise Interrupts in Pipelined Processors. IEEE Transactions on Computers, 37(5):562--73, May 1988.

....programming language, and then automatically convert that program into an equivalent concurrent program by techniques that are known to be correct. There are two relatively standard approaches for converting sequential imperative programs into equivalent concurrent programs, Tomasulo s algorithm [117, 57, 104, 83, 105], and compiler based program restructuring based on a technique called scalar expansion [68] Each of these techniques presents the architect with a set of tradeoffs. In particular, Tomasulo s algorithm guarantees the elimination of register storage dependences, and is relatively easily extended ....

....to some functional program [72, 58, 7] Since a functional program never overwrites any part of an object (but rather creates an entirely new object) there are no storage dependences. Another way to view the result is in terms of the dynamic register renaming performed by Tomasulo s algorithm [117, 57, 104, 83, 105]. Tomasulo s algorithm performs a dynamic mapping of virtual register names to physical registers, each of which is written only once. After this renaming all register storage dependences are eliminated, because (conceptually) no physical register ever changes its value. Thus, the instruction ....

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James E. Smith and Andrew R. Pleszkun. Implementing precise interrupts in pipelined processors. IEEE Transactions on Computers, 37(5):562--573, May 1988.

.... contains only safe data (Eager or Lazy AMM) or it can contain speculative data as well (FMM) To help understand this difference, we use an analogy with the concepts of architectural file, reorder buffer, future file, and history buffer proposed by Smith and Pleszkun for register file management [19]. The architectural file in [19] refers to the safe contents of the register file. The architectural file is updated with the result of an instruction only when the instruction has completed and all previous instructions have already updated the architectural file. The reorder buffer allows ....

.... or Lazy AMM) or it can contain speculative data as well (FMM) To help understand this difference, we use an analogy with the concepts of architectural file, reorder buffer, future file, and history buffer proposed by Smith and Pleszkun for register file management [19] The architectural file in [19] refers to the safe contents of the register file. The architectural file is updated with the result of an instruction only when the instruction has completed and all previous instructions have already updated the architectural file. The reorder buffer allows instructions to execute speculatively ....

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J. E. Smith and A. R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors. IEEE Trans. Computers, C-37(5):562--573, May 1988.

....issuing techniques, developed over the past three decades, can be brought to bear on this task. Exmnples include the CDC 6600 scoreboard [18, 19] the register renaming scheme, known as Tomasulo s algorithm, incorporated in the IBM 360 91 [2, 20] the history file, reorder buffer and future file [15], the register update unit [16] and checkpoint repair [9] The conventional wisdom is that dynamic scheduling using such techniques is inapplicable to VLIW processors. The primary objective of this paper is to show that this view is wrong, that dynamic scheduling is just as viable 1072 4451 93 ....

Smith, ,I.E., and Pleszkun, A.R. Implementing precise interrupts in pipelined processors. IEEE Transactions on Computers C-37, 5 (May 1988), 562-573.

.... (complex implementations with a slow clock) controversy [Gwe93] The mid 1990s saw some convergence between the two camps. Almost all vendors moved towards designs implementing complex out of order microarchitectures based on the 6600 and 360 91 schemes as well as ideas explored in academia [SP88, Soh90, HP86, YP92] At the time of the writing of this thesis, every major microprocessor vendor has a product implementing sophisticated dynamic scheduling. In 1996, Digital Equipment Corporation, long considered to be the bastion of the speed demons, announced plans for a product (DEC 21264 ....

J. E. Smith and A. R. Pleszkun. Implementing precise interrupts in pipelined processors. IEEE Transactions on Computers, 37:562--573, May 1988.

....respectively, relative to an aggressive conventional architecture. We also describe how Cherry and speculative multithreading can be combined and complement each other. 1 INTRODUCTION Modern out of order processors typically employ a reorder buffer (ROB) to retire instructions in order [18]. In order retirement enables precise bookkeeping of the architectural state, while making out of order execution transparent to the user. When, for example, an instruction raises an exception, the ROB continues to retire instructions up to the excepting one. At that point, the processor s ....

.... Specifically, processor execu No Return Head (oldest) Head (oldest) Irreversible Reversible Reversible Cherry ROB Conventional ROB Point of Figure 1: Conventional ROB and Cherry ROB with the Point of No Return (PNR) We assume a circular ROB implementation with Head and Tail pointers [18]. tion seamlessly falls back to non Cherry mode (Section 2.1) Then, the interrupt is processed. After that, the processor can return to Cherry mode. The position of the PNR depends on the particular implementation and the types of resources recycled. Conservatively, the PNR can be set to the ....

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J. E. Smith and A. R. Pleszkun. Implementing precise interrupts in pipelined processors. IEEE Transactions on Computers, 37(5):562-- 573, May 1988.

....a lot. For a better performance and hardware utilization, many designs therefore allow the rearranging of instructions (out of order execution) The instruction execution and the resources are then governed dynamically by hardware schedulers, most of which are based on the result shift register [26], the Scoreboard [28] and the Tomasulo Algorithm [29] One major difference between the schedulers is how early in the processing they allow instructions to leave the in order execution. In case of out of order completion, the instructions and their operands are passed to the functional units ....

....FU is already started out of order. Since hardware schedulers are widespread nowadays [2, 5, 7, 9, 10, 11, 24, 27] one would aspect plenty of studies which quantify the impact of the different type of schedulers on the performance and cost (gate count) of processors. However, the open literature [16, 12, 26] rather focus on the impact of design changes. For a partially supported by the German Science Foundation DFG supported by the DFG graduate program Effizienz und Komplexit at von Algorithmen und Rechenanlagen given scheduler, they study the speedup gained by varying the degree of ....

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J.E. Smith and A.R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors. IEEE Transactions on Computers, 37(5):562-- 573, 1988.

....prediction. In addition to that, we implemented precise interrupts in a five stage DLX by speculating that an interrupt does not happen. The truth is detected in stage 4 at the latest. In case of a misspeculation, the pipeline is cleared using the rollback mechanism. This concept is taken from [23]. 6. FORMAL VERIFICATION 6.1 Pipeline Properties We verified the correctness of the generated machines using the theorem proving system PVS [8] This comprises both data consistency and liveness. The data consistency criterion is taken from [20] Let I 0 # I 1 #### denote an instruction ....

J. Smith and A. Pleszkun. Implementing precise interrupts in pipelined processors. IEEE Transactions on Computers, 37(5):562--573, 1988.

....the Exemplar. 2 Background 2.1 Read Miss Clustering Instructions in an out of order processor s instruction window (reorder buffer) can issue and complete out oforder. To maintain precise interrupts, however, instructions commit their results and retire from the window in order after completion [30]. The only exception is for writes, which can use write buffering to retire before completion. Because of the growing gap in processor and memory speeds, external cache misses can take hundreds of processor cycles. However, current out of order processors typically have only 32 80 element ....

J. E. Smith and A. R. Pleszkun. Implementing precise interrupts in pipelined processors. IEEE Trans. on Computers, C-37(5):562--573, May 1988.

....processed in the instruction window (reorder buffer) of an out of order issue processor. Instructions in the window can issue and complete outof order. However, to maintain precise interrupts, instructions must commit their results and retire from the window in program order after completion [SP88] Stores may retire before completing at the memory hierarchy in systems that support write buffering. As described in Section 2.1, an external cache miss may require hundreds of proces 16 Load Add Add Load Add Load fetch retire (a) Miss latency exposed Load Add Add Load Add Load fetch ....

J. E. Smith and A. R. Pleszkun. Implementing precise interrupts in pipelined processors. IEEE Transactions on Computers, C-37(5):562--573, May 1988.

.... the preferred techniques are ones which do not rely on fixed timing for their correct operation, such as branch prediction schemes [12] 20] or advanced branching mechanisms [15] Precise exception handling and speculative execution are supported through the use of history and write back buffers [21] [23] A micronet based datapath, as illustrated in Figure 2, is composed of a network of microagents (denoted by solid boxes) which are connected via ports. The Functional Microagents (FMs) perform microoperations which are typical of a datapath. On each port of a FM is a Communicating ....

J. E. Smith and A. R. Pleszkun. Implementing precise interrupts in pipelined processors. IEEE Transactions on Computers, 37(5):562--573, May 1988.

....program execution such as arithmetic overflows, memory protection violations, I O calls or operating system calls, etc. Several solutions to the interrupt problem have been proposed for the interrupt problem for out of order processors such as the reorder bu#er, the history bu#er, the future file [153], checkpoint repair [74] and current state bu#er [111] All issues related to exceptions and exception handling mechanisms are left for future work on AEPIC architecture. 5.7 Summary AEPIC is a candidate architecture from the CAEP IC space of architectures that we have identified as a suitable ....

James E. Smith and Andrew R. Pleszkun. Implementing precise interrupts in pipelined processors. IEEE Transactions on Computers, 37(5):562--573, May 1988.

....can possibly use the old destination register, so it can be reused. Up to this point, there exists the possibility that restoring a checkpointed RegMap that maps a logical register to the old physical register can revive this physical register. This architecture uses precise exceptions [17]. Exceptions, which occur during the execution of an instruction in the out oforder core, are stored together with the result of the instruction. They are not signaled until an instruction is ready to retire. This allows (1) the exact register state to be restored for the exception handler and (2) ....

J. E. Smith and A. R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors. IEEE Transactions on Computers, 37(5):562--573, May 1988.

....the results of all speculatively instructions that Fundamentals of Instruction Level Parallel Processing 19 depend on the branch are updated. If the prediction was incorrect, then the results are discarded. Several dynamic techniques have been proposed to implement speculatively execution [SV87, SP87] Implementing speculative execution in hardware can be expensive. The alternative is to perform speculative code motion at compile time. Operations from subsequent basic blocks are moved to preceding basic blocks. These operations will execute before the branch that they were supposed to ....

J.E. Smith and A.R. Pleszkun. Implementing precise interrupts in pipelined processors. IEEE Trans. on Comps., 37(5):562--573, May 1987.

....of this is shown in Figure 4. The dependence check logic detects such dependences and sets up the output MUXes so that the appropriate physical register designators are generated. The shadow table is used to checkpoint old mappings so that the processor can quickly recover to a precise state [27] from branch mispredictions . At the end of every rename operation, the map table is updated to reflect the new logical to physical mappings created for the result registers written by the current rename group. SLICE) LOGIC CHECK DEPENDENCE MAP TABLE SHADOW ....

J. E. Smith and A. R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors. IEEE Transactions on Computers, 37:562--573, May 1988.

....of this is shown in Figure 5. The dependence check logic detects such dependences and sets up the output MUXes so that the appropriate physical register designators are generated. The shadow table is used to checkpoint old mappings so that the processor can quickly recover to a precise state [27] from branch mispredictions . At the end of every rename operation, the map table is updated to reflect the new logical to physical mappings created for the result registers written by the current rename group. MAP TABLE SHADOW TABLE pregil CHECK LOGIC (SLICE) pregWr MUX preg1l ....

J. E. Smith and A. R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors. IEEE Transactions on Computers, 37:562--573, May 1988.

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James E. Smith and Andrew R. Pleszkun. Implementing precise interrupts in pipelined processors. IEEE Transactions on Computers, 37(5):562--573, May 1988.

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J. E. Smith and A. R. Plezkun. Implementing precise interrupts in pipelined processors. IEEE Transactions on Computers, C-37(5):562--573, May 1988.

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J. E. Smith and A. R. Pleszkun. Implementing precise interrupts in pipelined processors. IEEE Trans. on Computers, C-37(5):562--573, May 1988.

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Smith J.E., Pleszkun A.R. Implementing precise interrupts in pipelined processors. IEEE Transactions on Computers, 37(5):562--573, Sep 1988.

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James E. Smith and Andrew R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors. IEEE Transactions on Computers, C-37(5):562--573, May 1988.

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J.E. Smith and A.R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors. IEEE Transactions on Computers, 37(5):562--73, May 1988.

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James E. Smith and Andrew R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors. IEEE Transactions on Computers, C-37(5):562--573, May 1988.

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J. E. Smith and A. R. Pleszkun, "Implementing Precise Interrupts in Pipelined Processors", in IEEE Trans. on Computers, Vol. 37, NO. 5, May 1988.

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J. E. Smith and A. R. Pleszkun, "Implementing Precise Interrupts in Pipelined Processors", in IEEE Trans. on Computers, Vol. 37, NO. 5, May 1988.

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