C. N. Coelho Jr. and G. De Micheli. Analysis and synthesis of concurrent digital circuits using control-flow expressions. Technical report, Stanford University, 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....based notation. Hierarchy is expressed using a regular grammar. This is the same approach as that taken by Clairvoyant. The way in which the derivatives are calculated in their approach resembles the way that Control Flow Expressions are calculated as introduced by Coelho and DeMicheli in [67]. 3.2.5. ProGram Port Size Independent Specifications Our approach [paper I VIII] is similar to the Clairvoyant PC and the Interface based Design approaches to the extent that the input is a production based specification and the output is in RT level VHDL. However, they differ in notation ....

....algebras, like LOTOS [24] LOTOS has many constructs that are similar to ProGram s in many respects. LOTOS is also a formal language, so finding common cross points between ProGram and LOTOS is a good starting point in defining a formal semantics for ProGram itself. Control flow expressions [67], is another good starting point. It is a subset of a process algebra and it is targeted for describing control flow intensive designs like data communication protocols. Many of the algebraic constructs have a direct relation to the internal representation used in ProGram. Also, some of the ....

C.N. Coelho, G. deMicheli, "Analysis and synthesis of concurrent digital circuits using control-flow expressions", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 15, No. 8, pp. 855-876, Aug. 1996.

....We implement our run time scheduler as follows. From the main task, we extract a CDFG specifying the control flow of tasks. Since we assume that the main task in invoked at a fixed rate, the CDFG we obtain is also invoked at a fixed rate. The CDFG has an equiv alent Control Flow Expression[22] which is used to synthesize a hardware FSM[16, 18] This FSM implements the overall system control and can predictably meet the relative timing constraints, if satisfiable, specified in exact numbers of cycles between the start times of tasks, which we hypothesize cannot be satisfied by ....

....into two parts: An executive manager in hardware with cyclebased semantics that can satisfy hard real time constraints. A software scheduler that executes different threads (software tasks) based on the start vector. We have described the synthesis of the hardware execu tive manager in [16, 22, 18, 19]. In this paper we focus on the generation of conditional edges which allow our run time scheduler to implement path based edge activation and thereby make WCET as small as possible. because the execution time of each node in a NEVER set depends upon the scheduling of the other nodes in the NEVER ....

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C. N. Coelho Jr. and G. De Micheli, "Analysis and Synthesis of Concurrent Digital Circuits Using Control-Flow Expressions," IEEE Transactions on CAD/ICAS, Vol. 15, No. 8, August 1996.

....or synchronous reactive models [20] The nesting is arbitrarily deep and can mix concurrency models at different levels of the hierarchy. This very flexible model is called charts, pronounced star charts, where the asterisk is meant to suggest a wildcard. Control Flow Expressions (CFEs, [21]) have been recently proposed to represent the control flow of a set of operations in a cycle based specification language. CFEs are an algebraic model extending Regular Expressions [9] and can be compiled into FSMs that can be used in the synthesis of a control unit. B.3 Synchronous Reactive In ....

Jr C. N. Coelho and G. De Micheli, "Analysis and synthesis of concurrent digital circuits using control-flow expressions," IEEE Trans. on CAD, vol. 15, no. 8, pp. 854--876, Aug. 1996.

.... (see, e.g. 15] Code synthesis for control dominated applications, in which rapid reaction to external events and complex decision mechanisms dominate over pure data computations, require software or hardware to be efficiently synthesized from Finite State machine like specifications [3, 13, 9, 8]. The aim of this paper is to exploit don t care (DC) information (coming, e.g. from impossible or irrelevant conditions limited controllability) in software code synthesis. The use of DCs, to the best of our knowledge, has been limited so far only to hardware synthesis [11] Note that some ....

C.N. Coelho and G. De Micheli. Analysis and Synthesis of Concurrent Digital Circuits using Control-flow Expressions. IEEE Transactions on Computer-Aided Design, 15(8), pp. 854-876, August 1996.

....main task, intermediate task(s) and leaf tasks, we flatten the description until we have a single TaskSIF graph. Since we assume that the main task in invoked at a fixed rate, the TaskSIF graph we obtain is also invoked at a fixed rate. The TaskSIF graph has an equivalent Control Flow Expression[23] which is used to synthesize a hardware FSM[19] This FSM implements the overall system control and can predictably meet the relative timing constraints, if satisfiable, specified in exact numbers of cycles between the start times of tasks, which we hypothesize cannot be satisfied by software. ....

....in hardware with cycle based semantics that can satisfy hard real time constraints. ffl A preemptive static priority scheduler that executes different threads based on eligible software tasks as indicated by the start vector. We have described the synthesis of the hardware executive manager in [19, 23]. In this paper we focus on the generation of a priority scheduler for the software tasks. 4.2 Priority Scheduler Template for Software A task can be in one of four distinct states: ready, running, suspended, or terminated. We accomplish this with a single ready list, implemented as a linked ....

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C. N. Coelho Jr. and G. De Micheli, "Analysis and Synthesis of Concurrent Digital Circuits Using Control-Flow Expressions," IEEE Transactions on CAD/ICAS, Vol. 15, No. 8, August 1996 . 9

....described in terms of a process algebra with data and absolute timing. Unfortunately, a high degree of abstraction has also a drawback. It is very dicult to automatically produce cost ecient hardware. Di erent proposals starting from process algebra speci cations have been made[Mar86, PL91, SZ95, Cd96] Most of them produce hardware by a direct compilation of the process algebra terms into hardware blocks. In 1 COPERNICUS Project COPRODES Nr. CP 940453 of the European Community 2 Riga Aeronautical University, Technical University of Prague, Technical University of Budapest, ASICcentrum ....

C. N. Coelho and G. deMicheli. Analysis and synthesis of concurrent digital circuits using control- ow expressions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(8):855-876, August 1996.

....We implement our run time scheduler as follows. From the main task, we extract a CDFG specifying the control ow of tasks. Since we assume that the main task in invoked at a xed rate, the CDFG we obtain is also invoked at a xed rate. The CDFG has an equivalent Control Flow Expression[22] which is used to synthesize a hardware FSM[16, 18] This FSM implements the overall system control and can predictably meet the relative timing constraints, if satis able, speci ed in exact numbers of cycles between the start times of tasks, which we hypothesize cannot be satis ed by software. ....

....into two parts: 4 An executive manager in hardware with cyclebased semantics that can satisfy hard real time constraints. A software scheduler that executes di erent threads (software tasks) based on the start vector. We have described the synthesis of the hardware executive manager in [16, 22, 18, 19]. In this paper we focus on the generation of conditional edges which allow our run time scheduler to implement path based edge activation and thereby make WCET as small as possible. 5 Real Time Analysis We aim to predictably satisfy real time constraints in the form of control ow (precedence ....

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C. N. Coelho Jr. and G. De Micheli, \Analysis and Synthesis of Concurrent Digital Circuits Using Control-Flow Expressions," IEEE Transactions on CAD/ICAS, Vol. 15, No. 8, August 1996.

....the specific problem of interface synthesis is not addressed. The use of derivatives of regular expressions was introduces by Brzozowski [5] The particular way in which the derivatives are computed in our work resembles that introduced by Coelho et al. in their work on control flow expressions [6]. 3 Protocol specification As stated in the general problem formulation, the input to the algorithm is a description of the protocol used by the two modules. In our case, we assume that each module has a set of ports (data and control) over which the transfer occurs. We define a protocol as the ....

C. N. Coelho and G. D. Micheli. Analysis and synthesis of concurrent digital circuits using control-flow expressions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(8):854--876, August 1996.

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C. N. Coelho Jr. and G. De Micheli. Analysis and synthesis of concurrent digital circuits using control-flow expressions. Technical report, Stanford University, 1994.

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C. N. Coelho Jr. and G. De Micheli, "Analysis and Synthesis of Concurrent Digital Circuits Using ControlFlow Expressions," IEEE Transactions on CAD/ICAS, Vol. 15, No. 8, pp. 854--876. August 1996, and Technical Report CSL-TR-96-694, http://elib.stanford.edu/Dienst/UI/2.0/Describe/stanford.cs%2fCSL-TR-96694, Stanford, CA, April, 1996.

....[10] but with the difference that these expressions are used to guide the synthesis tool during the synthesis, and not as watchdogs during simulation. We will consider in this paper only synchronization and scheduling constraints. Binding and more complex constraint specifications can be found in [8]. In the following example, we show how to represent constraints in control flow expressions by means of the specification of synchronization sets and by a quantification of the design space. Example 2 [Synchronization Constraints] In the Example 1, the routine enqueue synchronizes with some ....

....time. This set is called here the NEVER set. In this example, NEVER = a, a , since no two bus accesses should execute at the same time (similarly, we have a synchronization constraint specifying that a multiset of actions should always execute at the same time, and we call this set the ALWAYS set [8]) In addition to considering the synchronization sets represented by the ALWAYS and NEVER sets, we also represent quantitatively the design space in control flow expressions by decision variables. Example 3 [Decision Variables] In the case we want to syn thesize the synchronization between ....

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C. N. Coelho Jr. and G. De Micheli. Analysis and synthesis of concurrent digital circuits using control-flow expressions. Technical report, Stanford University, 1994.

.... resources and registers [13] We assume here that the degrees of freedom introduced by the software are considered during the hardware synthesis process in order to further optimize the hardware implementation and also to reduce the need for additional synchronizations, as described in general by [10, 11]. For example, hardwaresoftware I O transfers (also called in this paper HSI O) in a thread that are performed in parallel in the specification can be collapsed and serialized to share the same register port. Strict timing constraints obtained from the HSI Os can also be used in the hardware to ....

....Si and Si , and obtain the minimum number of threads that includes the changes between the two specifications. In order to be compared, both specifications are abstracted into their control flow expressions, which are an abstraction of the control flow of any hardware description language [10, 11]. 5.1 Control Flow Expressions Control flow expressions is an algebra used to model the control flow of a specification, by abstracting away data flow information. The data flow is abstracted in terms of its execution time mapping, which is assumed in this paper to be one clock cycle for each ....

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C. N. Coelho Jr. and G. De Micheli. Analysis and synthesis of concurrent digital circuits using control-flow expressions. Technical report, Stanford University, 1994.

....constraints at the task level must be handled by the run time system. How can the run time system dynamically allocate tasks while at the same time predictably satisfying exact timing constraints between tasks We solve this scheduling problem using the algebra of control flow expressions (CFEs) [9], which represent the serial parallel flow of computation, branching, iteration, synchronization and exceptions. CFEs can specify control flow that satisfies our real time constraints in hardware while also controlling dynamically the flow of execution. CFEs have a deterministic finite state ....

....is used to delay the execution of mvm1 in the case that c3 is asserted while mvm2 is still executing. This works provided mvm2 is always executed before mvm1. A more general way of providing for mutually exclusive dynamic granting of start events for the same resource is to use the CFE NEVER sets[9]. 2 The CFE of the root task guides the composition of the extracted CFEs. If the input tasks are a complete set for the system, then Serra will successfully collapse all the extracted CFEs into the root CFE. Example 3[CFE Composition] To implement the hardware portion of the run time scheduler, ....

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C. N. Coelho Jr. and G. De Micheli, "Analysis and Synthesis of Concurrent Digital Circuits Using Control-Flow Expressions," IEEE Transactions on CAD/ICAS, Vol. 15, No. 8, August 1996 .

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C. N. Coelho Jr. and G. De Micheli, "Analysis and Synthesis of Concurrent Digital Circuits Using Control-Flow Expressions," IEEE Transactions on CAD/ICAS, Vol. 15, No. 8, August 1996 .

....model of computation is the same, and we subset both languages to support only synthesizable constructs. Our synthesis system, called Parnassus synthesis system, targets control dominated applications, and leverages previous research on modeling hardware using control flow expressions (CFEs) [12, 13]. In Parnassus, CFEs represent an intermediate model applicable to both Verilog modules and C programs, that captures the global control flow information in the system. Parnassus converts the input specifications into CFEs, and then synthesizes the corresponding datapath and control unit. ....

....take an integer number of cycles (possibly unbounded) to execute. Branching decisions are taken instantaneously, and iterations take also an integer number of cycles (possibly zero or unbounded) The control flow of the system being modeled is abstracted as a set of expressions, called CFEs [12], representing the serial parallel flow of computation, branching, iteration, synchronization and exceptions. Such expressions have a deterministic finite state machine (FSM) semantics, and can be compiled into specification FSMs representing the possible control flow implementations. In order to ....

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C. N. Coelho Jr. and G. De Micheli, "Analysis and Synthesis of Concurrent Digital Circuits Using ControlFlow Expressions," IEEE Transactions on CAD/ICAS, (to appear), and Technical Report CSL-TR-96-694, http://elib.stanford.edu/Dienst/UI/2.0/Describe/stanford. cs%2fCSL-TR-96-694, Stanford, CA, April, 1996.

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