R. K. Kolagotla, S.-S. Yu, and J. F. J&J&, "VLSI implementation of a tree searched vector quantizer", IEEE Tran. Signal Processing, vol. 41, No. 2, pp. 901-905, Feb. 1993. Home/Search Document Not in Database Summary Related Articles Check |
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Tree-Structure Architecture and VLSI Implementation - Quantization (Correct)
....fast operation ability and the support of smooth data flow are both important. Since VQ is both I O bound and com putation bound with poor data reuse, it is not easy to implement VQ in hardware. Some available works include bit serial approaches [1] multiply and accumulate (MAC) approach [2], and systolic array approach [3] In order to solve the realization problems such as large I O bandwidth, complicated hardware, and irregular da ta flow, etc. most of the previous approaches change data sequence to alleviate these problems while sacrificing latency and throughput at the same ....
....B, is added to produce the correct result. Unfortunately, the full tree architecture can not be implemented due to its huge input bandwidth and chip size. Large amount of memory modules and pin count are caused and it is impossible to fulfil the full tree architecture. Some pre vious works [1][2] change data flow for implementation. In Figure 2 (a) the data flow of bit serial approach is demostrated. The sixteen multipliers are substituted by serial parallel multipliers. As a result, the bandwidth of input and the complexity of multipliers are both reduced. The disadvantages of bit serial ....
R. K. Kolagotla, S.-S. Yu, and J. F. J&J&, "VLSI implementation of a tree searched vector quantizer", IEEE Tran. Signal Processing, vol. 41, No. 2, pp. 901-905, Feb. 1993.
Variable-Precision Arithmetic for Vector Quantization - Dionysian (1994) (Correct)
....detection. It is currently under investigation for image compression, where it outperforms the current standard by Joint Picture Experts Group (JPEG) There is also a strong interest in dedicated hardware for VQ. Several integrated circuits have been implemented specifically for VQ [DG86, FCS90, KYJ93, DJK92, DB87] Problem: Vector Quantization Vector quantization finds in a set of codevectors the vector most similar to the source vector, a sequence of digitized signal samples. Applications other than compression also require such a dedicated engine: VQ has been used in segmenting images ....
.... VQ 1986 Nelson [NR86] 9 MSE serial VQ 1987 Abut [ATS87] 8 MSE parallel VQ 1987 Dionysian[DB87] 7 IP parallel VQ 1988 Davidson[DCG88] 12 IP parallel VQ 1989 Ramamoorthy [RPT89] 9 MSE serial VQ 1990 Fang [FCS90] 8 IP parallel TSVQ 1992 Dezhgosha [DJK92] 9 MAD parallel VQ 1993 Kolagotla [KYJ93] 8 IP parallel TSVQ on the application. Image pixels used in VQ compression are 8 bits. Depending on the preprocessing, its precision could increase to 9 or 10 bits. Meanwhile, speech samples are 12 bits. Several chips directly evaluate sum of square of difference distance. A VLSI ....
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R. K. Kolagotla, S. S. Yu, and J. F. JaJa. VLSI implementation of a tree searched vector quantizer. IEEE Trans. Signal Processing, pages 901--905, February 1993.
Low Power Design of Memory Intensive Functions Case Study.. - Lidsky, Rabaey (1994) (Correct)
....cycles making it impossible to process more then one vector at a time. Therefore methods to reduce the critical path, such as pipelining and parallelism, can not be implemented without duplicating the entire memory. If the memory is partitioned, however, and a distributed memory approach is used [7], pipeline stages can be introduced, enabling reductions in voltage, clocking frequency, and switching capacitance. The distributive memory architecture is discussed in a later section. Memory Architecture: For each vector comparison, there are sixteen eight bit words that must be accessed. A ....
....due to the larger interconnect capacitance. Distributive Memory: In TSVQ each level of a tree has specific codevectors associated with it, and the codevectors from each level are found only at that level. Therefore the memory can be partitioned into separate memories for each level of the tree[7]. Associated with each memory are identical processing elements and controllers. With this architecture, a pipelined structure may now be utilized and the critical path is reduced drastically (figure 5) The chip can now process eight vectors simultaneously with only a negligible increase in ....
R. Kolagotla, et al, "VLSI Implementation of a Tree Searched Vector Quantizer," IEEE Trans. on Signal Proc., vol. 41, no 2, February 1993
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