L. Claesen, et al., "Automatic synthesis of signal processing benchmark using the CATHEDERAL silicon compilers," IEEE Custom Integrated Circuits ConJ&rence, pp. 14.7.1- 4.7.4, 1988.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....in them. Haroun and Elmasry in [50] present SPAID: A novel design methodology for DSP algorithm synthesis. Various transformations in SPAID include pipelining, retiming etc which made it an efficient synthesis engine of its time. Another very important high level synthesis system was Cathedral [22], 15] It takes behavioral descriptions written in Silage and generates optimized hardware targeting specific forms of implementations. Hyper [6] 20] is completely integrated another high level synthesis system that takes behavioral descriptions written in Silage and is driven towards real time ....

L. Claesen, F. Catthoor, D. Lanneer, G. Goossens, S. Note, J. van Meerbergen, and H. de Man . " Automatic Synthesis of Signal Processing Benchmarks Using the CATHEDRAL Silicon Compilers ". In Proc. IEEE Custom Integrated Circuits Conference, 1988.

....and latency minimization) were first illustrated (and sometimes even motivated and justified) by presenting the implementations of this example. However, even a brief analysis of the 5th order elliptical WDF reveals many unpleasantly surprising facts. The example was first used by Dewilde [DDN85] and in 1988 the IMEC group presented the full implementation of this example according to CCITT standards [C 88] They noted that the structure 6 is unnecessarily complex for the required transfer function. Sometimes functionally incorrect implementations were presented. The instances of the 5th order ....

L. Claesen et al. Automatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers. Custom Integrated Circuits Conference, 1988.

....and latency minimization) were first illustrated (and sometimes even motivated and justified) by presenting the implementations of this example. The example was first used by Dewilde [4] and in 1988 the IMEC group presented the full implementation of this example according to CCITT standards [3]. However, even a brief analysis of the 5th order elliptical WDF reveals many peculiar properties for a benchmark. For example, a study of several hundred DSP examples indicated that the 5th order elliptical WDF is the only example where all nodes are in cycles and where the critical path was from ....

....of operations over time. Since wave digital filters are widely recognized as exceptionally numerically stable, it is exceptionally sensitive on the application of computational transformations. It was also noted that the structure is unnecessarily complex for the required transfer function [3]. In the outset, some authors used functionally incorrect implementations. The instances of the 5th order elliptical WDF where some operations were simply deleted have been published. Some authors simply remove feedback edges, which does not result only in functionally incorrect implementations ....

L. Claesen et al. Automatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers. Custom Integrated Circuits Conference, pages 14.7.1--14.7.4, 1988.

....model of computation is the homogeneous synchronous data flow model of [Lee87] The ASIC hardware model being considered is shown in Figure 1. This model, the dedicated register model, clusters all registers in register files, connected only to the inputs of the corresponding execution units [Cla88]. We also assume that there is no bus merging, so there exists a dedicated bus connecting any two units between which there are data transfers. Note that the HBISR methodology itself is not limited to this hardware model; generalizations are discussed in Section 7.0. 3.2 Fault Model, Detection, ....

L. Classen, et al., "Automatic Synthesis of Signal Processing Benchmarks using the CATHEDRAL Silicon Compilers," IEEE CICC, pp. 14.7.1-14.7.4, 1988.

....and latency minimization) were first illustrated (and sometimes even motivated and justified) by presenting the implementations of this example. The example was first used by Dewilde [4] and in 1988 the IMEC group presented the full implementation of this example according to CCITT standards [3]. However, even a brief analysis of the 5th order elliptical WDF reveals many peculiar properties for a benchmark. For example, a study of several hundred DSP examples indicated that the 5th order elliptical WDF is the only example where all nodes are in cycles and where the critical path was ....

....of operations over time. Since wave digital filters are widely recognized as exceptionally numerically stable, it is exceptionally sensitive on the application of computational transformations. It was also noted that the structure is unnecessarily complex for the required transfer function [3]. In the outset, some authors used functionally incorrect implementations. The instances of the 5th order elliptical WDF where some operations were simply deleted have been published. Some authors simply remove feedback edges, which does not result only in functionally incorrect implementations ....

L. Claesen et al. Automatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers. Custom Integrated Circuits Conference, pages 14.7.1--14.7.4, 1988.

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L. Claesen, et al., "Automatic synthesis of signal processing benchmark using the CATHEDERAL silicon compilers," IEEE Custom Integrated Circuits ConJ&rence, pp. 14.7.1- 4.7.4, 1988.

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