Motorola Inc. 1994. PowerPC 604: RISC Microprocessor User's Manual. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Continuous Program Optimization: A Case Study - Kistler, Franz (2003) (4 citations) (Correct)
....et al. 1997; Zhang et al. 1997] and hardware based solutions [Dean et al. 1997; Conte et al. 1996] The last of these is obviously the most desirable and will become increasingly important in future microprocessors. As an example, while the 601 and 603 models of the PowerPC processor family [Motorola Inc. 1997] do not provide built in profiling support, the PowerPC 604 is now equipped with a performance monitor. This performance monitor includes two 32 bit hardware counters that facilitate monitoring detailed events during execution, such as instruction dispatches, instruction cycles, misses in ....
....line would actually be filled in the order 003, 004, 005, 006, 007, 000, 001, 002; i.e. it would take at least seven additional cycles from the time at which the contents of location 003 become available until the contents of 002 become available also. On processors such as the PowerPC 604e [Motorola Inc. 1996] that forward the contents of the cache line fill bu#er to a requesting load unit immediately upon availability, it can hence make a di#erence whether the predominant memory access pattern is 003 followed by 002, or vice versa. Finding an optimal ordering of fields within cache lines is ....
[Article contains additional citation context not shown here]
Motorola Inc. 1994. PowerPC 604: RISC Microprocessor User's Manual.
Multiple-Block Ahead Branch Predictors - Seznec, Jourdan, Sainrat, Michaud (1996) (32 citations) (Correct)
....in table 1 of such out oforder architectures give almost no performance loss over perfect configurations only limited by the size of the lookahead window, assuming an ideal fetch mechanism and no misprediction. The instruction latencies used in the simulations were those of the PowerPC 604 [11]. The mean IPC values varied from 3.6 to 6.5 on integer programs according to the dispatch width (4, 6, and 8 instructions dispatched per cycle) We keep their configurations (DW 4, DW 6 and DW 8) in order to evaluate the fetch mechanisms. The lookahead window is the maximum number of dispatched ....
IBM and Motorola, "PowerPC 604 RISC Microprocessor User's Manual," MPR604UMU-01, 1994.
Multiple-Block Ahead Branch Predictors - Seznec, Jourdan, Sainrat, Michaud (1996) (32 citations) (Correct)
....in table 1 of such out of order architectures give almost no performance loss over perfect configurations only limited by the size of the lookahead window, assuming an ideal fetch mechanism and no misprediction. The instruction latencies used in the simulations were those of the PowerPC 604 [9]. The mean IPC values varied from 3.6 to 6.5 on integer programs according to the dispatch width (4, 6, and 8 instructions dispatched per cycle) We keep their configurations (DW 4, DW 6 and DW 8) in order to evaluate the fetch mechanisms. The lookahead window is the maximum number Parameters ....
IBM and Motorola, "PowerPC 604 RISC Microprocessor User's Manual," MPR604UMU-01, 1994.
A CMOS Floating Point Unit - Kelley, Postiff (1997) (Correct)
No context found.
IBM and Motorola. "PowerPC 604 RISC Microprocessor Users's Manual." MPR604UMU-01. IBM.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC