Citations: Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers

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S. Hellebrand, et al. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Trans. on Comp., vol. 44, No. 2, February 1995, pp. 223-233

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Reducing Test Data Volume Using LFSR Reseeding with Seed.. - Krishna And Nur (2002) (5 citations) (Correct)

....[Knemann 91] requires s max 20 bits to encode each test cube regardless of the number of specified bits in the test cube. Several techniques have been proposed to improve the encoding efficiency including using multiplepolynomial LFSRs [Hellebrand 92] Venkataraman 93] concatenating test cubes [Hellebrand 95a] using variablelength seeds [Zacharia 95, 96] Rajski 98a] using partial dynamic LFSR reseeding [Krishna 01] and using twodimensional compression combining LFSR reseeding and folding counters [Liang 01] The method proposed in this paper involves compressing the seeds that are used in LFSR ....

....with a statistical code versus encoding LFSR seeds that produce the test cubes as is proposed here. As can be seen, much greater encoding efficiency can be obtain by encoding the seeds. Note that better results could be obtained for the proposed procedure by using multiple polynomial LFSRs [Hellebrand 95a] to reduce the length of the seeds. Other variations of LFSR reseeding could similarly be combined with the proposed approach for seed compression. Another way to reduce the tester storage requirements when using a separate LFSR would be to first apply pseudo random patterns to detect the random ....

Hellebrand, S., J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, "Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," IEEE Transactions on Computers, Vol. 44, No. 2, pp. 223-233, Feb. 1995.

A Unified Approach to Reduce SOC Test Data Volume, Scan.. - Chandra, Chakrabarty (2003) (Correct)

....on chip. Another method based on tester based stimulus and response compression (OPMISR) has been shown to be very effective for testing large scan based circuits with limited input outputs (I Os) 13] Another way to reduce test data volume and testing time is to use built in self test (BIST) [14]. However, BIST can only be applied to SOCs if the IP cores in them are BIST ready. BIST also imposes an area penalty and it often requires additional design changes. Since most currently available IP cores are not BIST ready, the incorporation of BIST in them requires considerable redesign. A ....

S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, "Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers," IEEE Trans. Comput., vol. 44, pp. 223--233, Feb. 1995.

Low-Overhead Built-In Bist Reseeding - Ahmad Yamani And (Correct)

....the linear expansion of the contents of the LFSR into the scan chain. If there is any linear dependence between the equations, solving this system won t be possible. By adding 20 bits to Sma as the size of the LFSR, the probability of linear dependence drops to 1 in a million [Konemann 91] In [Hellebrand 95] a scheme was presented for using Multiple polynomial LFSRs (MP LFSRs) in BIST. Reseeding was used to target r.p.r. faults. The authors used MP LFSRs to reduce the probability of linear dependence. The main contribution of the work was in using a smaller LFSR of size Sma 4, where Sma is the ....

Hellebrand, S., J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, "Built-in Test for Circuits with Scan Based on Reseeding of MultiplePolynomial Linear Feedback Shift Registers," IEEE Transactions on Computers, Vol. 44, No. 2, pp. 223233, Feb. 1995.

Synthesis of Configurable Linear Feedback Shifter - Registers For Detecting (2001) (Correct)

....and or a fee. ISSS 01, October 1 3, 2001, Montreal, Quebec, Canada. Copyright2001 ACM 1 58113 418 5 01 00010. 5.00. There have been various BIST techniques based on pseudorandom testing [1,9] pseudo exhaustive testing [2,10,11] weighted random testing [3,12,13] and reseeding of LFSR [5 7]. These approaches offer different trade off among test data volume, test application time, hardware overhead and fault coverage. One of the most popular approaches is the pseudo random BIST, which employs an LFSR to generate a large number of test patterns with small hardware overhead. The major ....

....function P(V) Once the generating function and the initial state are fixed, the pattems produced are also determined. It also can not produce a sequence of deterministic ordered pattems that are required to detect the random pattem resistant faults. A number of the LFSR based techniques [5 7] have been developed to generate deterministic ordered test patterns but the encoding and decoding procedures and the implementation of control logic are relatively complex. A 2 D LFSR structure was presented in [8] This generator can generate a set of pre computed test vectors for detecting ....

S. Hellebrand, et al., "Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feed-back Shift Registers", IEEE Trans. on Comp., Vol. 44, No. 2, pp. 223-233, Feb. 1995.

Test Vector Encoding Using Partial LFSR Reseeding - Krishna, Jas, Touba (2001) (12 citations) (Correct)

....the encoding efficiency is still limited by the fact that most test cubes may have many fewer than Smax specified bits. Two approaches for addressing the problem related to the variance in the number of specified bits in the test cubes have been proposed. One involves concatenating test cubes [Hellebrand 95a] and the other involves using variable length seeds [Zacharia 95, 96] Rajski 98] The idea of concatenating test cubes was proposed in [Hellebrand 95a] Instead of expanding each seed into a single test cube, it involves expanding each seed into some fixed number of test cubes, j. This is ....

....problem related to the variance in the number of specified bits in the test cubes have been proposed. One involves concatenating test cubes [Hellebrand 95a] and the other involves using variable length seeds [Zacharia 95, 96] Rajski 98] The idea of concatenating test cubes was proposed in [Hellebrand 95a] Instead of expanding each seed into a single test cube, it involves expanding each seed into some fixed number of test cubes, j. This is done by loading each seed into an MP LFSR, and running the MP LFSR in autonomous mode to generate the next j test vectors. So the set of test cubes is ....

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Hellebrand, S., J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, "Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," IEEE Transactions on Computers, Vol. 44, No. 2, pp. 223-233, Feb. 1995.

Test Volume and Application Time Reduction through Scan.. - Bayraktaroglu, Orailoglu (2001) (17 citations) (Correct)

....however, the fault can affect only a few scan chains, as illustrated in figure 2. The decompression scheme and its implementation is discussed in the next section. 3. DECOMPRESSION HARDWARE Test cubes with a limited number of specified bits have been shown to be encodable with an LFSR seed [5, 9]. Encoding test cubes with LFSR seeds has been utilized in various contexts, such as storing a number of deterministic patterns on chip [5] or compressing deterministic test cubes [9] All such schemes are employed to encode a test cube corresponding to a scan chain as noted previously. A test ....

....in the next section. 3. DECOMPRESSION HARDWARE Test cubes with a limited number of specified bits have been shown to be encodable with an LFSR seed [5, 9] Encoding test cubes with LFSR seeds has been utilized in various contexts, such as storing a number of deterministic patterns on chip [5], or compressing deterministic test cubes [9] All such schemes are employed to encode a test cube corresponding to a scan chain as noted previously. A test vector is generated by shifting the least significant bit of the LFSR through a scan chain starting from a precomputed seed. In the proposed ....

S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois. Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers. IEEE Transactions on Computers, 44(2):223--233, February 1995.

Bit-Fixing in Pseudorandom Sequences for Scan BIST - Touba, McCluskey (2001) (6 citations) (Correct)

....the pseudorandom patterns is also used to generate deterministic test cubes (test patterns with unspecified inputs) by loading it with a computed seed. The number of bits that need to be stored is reduced by storing a set of seeds instead of a set of deterministic patterns. Hellebrand et al. 15] [17] proposed an improved technique that uses a multiple polynomial LFSR for encoding a set of deterministic test cubes. By merging and concatenating the test cubes, they further reduce the number of bits that need to be stored. Even further reduction can be achieved by using variable length ....

S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, "Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers," IEEE Trans. Comput., vol. 44, pp. 223--233, Feb. 1995.

RP-SYN: Synthesis of Random Pattern Testable Circuits with.. - Touba, McCluskey (1999) (1 citation) (Correct)

....probability of the r.p.r. faults so that they are no longer r.p.r. i.e. eliminate the r.p.r. faults) The test pattern generator can be modified by adding logic to weight the patterns [27] 30] 37] correlate the patterns [26] map the patterns [7] 33] 34] 36] or reseed the generator [18], 19] 38] For on chip generation, these approaches generally require significantly more overhead than modifying the circuit structure itself. This paper focuses on techniques for modifying the circuit structure to make it random pattern testable. Two general techniques have been proposed for ....

S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, "Built-in test for circuits with scan based on reseeding of multiplepolynomial linear feedback shift registers," IEEE Trans. Computers, vol. 44, pp. 223--233, Feb. 1995.

Reducing Test Data Volume Using External/lbist Hybrid Test.. - Das, Touba (2000) (8 citations) (Correct)

....in the scenario where logic BIST is used to test high performance designs. Techniques that target the pseudo random test pattern generator are the use of weighted pseudo random sequences [Muradali 90] using multiple polynomial linear feedback shift registers with reseeding [Venkataraman 93] Hellebrand 95] and STARBIST [Tsai 97] All these approaches assume complete on chip test, meaning the LBIST test patterns are the only test patterns applied. The assumption of complete on chip test in previous approaches led to large area overheads and or increased delay. However, to combat the increasing ....

....STUMPS architecture with a minor modification (as will be described in Sec. 2) The approach is entirely orthogonal to the earlier approaches to increase LBIST fault coverage (i.e. test point insertion or TPG modification) If needed, any of the techniques in [Muradali 90] Venkataraman 93] Hellebrand 95] Tamarapalli 96] Touba 96] and [Tsai 97] can be used in the proposed method to further boost fault coverage. Hybrid patterns represent a technique of getting the most out of pseudo random and deterministic test data by merging both into a single pattern. Pseudo random LBIST patterns require ....

Hellebrand, S., J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, "Built-In Test for Circuits with Scan Based on Reseeding of MultiplePolynomial Linear Feedback Shift Registers," IEEE Transaction on Computers, Vol. 44, No. 2, pp. 223233, Feb. 1995.

Postgraduate Study Report DC-PSR-2004-14 - Mixed-Mode Bist Based (Correct)

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S. Hellebrand, et al. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Trans. on Comp., vol. 44, No. 2, February 1995, pp. 223-233

Pseudorandom Testing -- A Study of the Effect of the Generator .. - Petr Fiser Hana (Correct)

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Hellebrand, S. et al.: Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Trans. on Comp., vol. 44, No. 2, February 1995, pp. 223233

Influence of the Test Lengths on Area Overhead in Mixed-Mode.. - Petr Fiser Hana (2004) (Correct)

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S. Hellebrand, et al., "Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers". IEEE Trans. on Comp., vol. 44, No. 2, February 1995, pp. 223-233

Pseudorandom Testability -- Study of the Effect of the - Generator Type Petr (Correct)

An Efficient Mixed-Mode Bist Technique - Petr Fiser Hana (2004) (Correct)

Test Application Time and Volume Compression Through.. - Rao, Bayraktaroglu.. (2003) (Correct)

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S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, "Built-in Test for Circuits with Scan Based on Reseeding of Multiple-polynomial Linear Feedback Shift Registers ", IEEE Transactions on Computers, vol. 44, n. 2, pp. 223-- 233, February 1995.

Models and Algorithms for Optimization Problems in Digital.. - Flores (2001) (Correct)

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Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, and Bernard Courtois. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Transactions on Computers, 44(2):223--233, February 1995.

RL-Huffman Encoding for Test Compression and Power.. - Nourani, Tehranipour (1995) (Correct)

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S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, "Built-In Test for Circuit with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," IEEE Trans. On Computer, vol. 44, pp. 223-233, 1995.

On Combining Pinpoint Test Set Relaxation and Run-Length Codes - For Reducing Test (Correct)

Efficient Seed Utilization for Reseeding based Compression - Erik Volkerink Subhasish (2003) (2 citations) (Correct)

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S. Hellebrand, J. Rajski, S Tarnick, S. Venkatraman and B. Courtois, "Built-in Test for Circuits with Scan Based Reseeding of Multiple Polynomial Linear Feedback Shift Registers", IEEE Transaction on Computers, vol. 44, No. 2, pp.223233, 1995.

Minimization of Boolean Functions - Fiser (2002) (Correct)

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Hellebrand, S. et al.: Built-In Test for Circuits with Scan Based on Reseeding of Mult iple-Polynomial Linear Feedback Shift Registers. IEEE Trans. on Comp., vol. 44, No. 2, February 1995, pp. 223-233

RP-SYN: Synthesis of Random Pattern Testable Circuits with.. - Touba, McCluskey (1999) (1 citation) (Correct)

Synthesis Techniques for Pseudo-Random Built-In Self-Test - Touba (1996) (5 citations) (Correct)

Altering A Pseudo-Random Bit Sequence For Scan-Based BIST - Touba, McCluskey (1996) (25 citations) (Correct)

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Hellebrand, S., J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, "Built-In Test for Circuits with Scan Based on Reseeding of MultiplePolynomial Linear Feedback Shift Registers," IEEE Transactions on Computers, Vol. 44, No. 2, pp.#223-233, Feb. 1995.

Special ATPG to Correlate Test Patterns for.. - Karkala, Touba.. (1998) (Correct)

Virtual Scan Chains: A Means for Reducing Scan Length in Cores - Jas, Pouya, Touba (2000) (7 citations) (Correct)

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Hellebrand, S., J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, "Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," IEEE Transactions on Computers, Vol. 44, No. 2, pp. 223-233, Feb. 1995.

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