Muller H. L.: Simulating Computer Architectures. PhD thesis, Dept. of Comp. Sys, Univ. of Amsterdam 1993  Home/Search   Document Details and Download   Summary   Related Articles   Check

....options, such as a shared memory interface, will be considered as future work. 5. THE ARCHITECTURE LAYER The Sesame architecture models, which simulate the timing consequences of the events generated by an application model, are implemented in the Pearl discrete event simulation language [13]. This is a small but powerful object based language which provides easy construction of (abstract) architecture models and fast simulation. It has a C like syntax with a few additional primitives for simulation purposes. Architectures are modeled as communicating components (i.e. Pearl objects) ....

H. Muller. Simulating computer architectures. PhD thesis, Dept. of Computer Science, Univ. of Amsterdam, Feb. 1993.

....generates a trace event describing the computational activity of a Kahn process. These trace events may be coarse grain, such as execute a Discrete Cosine Transform (DCT) B. Architecture modeling The Sesame architecture models are implemented in the discrete event simulation language Pearl [9]. This is a relatively small but powerful object based language which has specifically been designed with the purpose of (abstract) computer architecture modeling in mind. As a consequence, Pearl has shown to be extremely suitable for easily and quickly building new or extending existing ....

H. L. Muller. Simulating computer architectures. PhD thesis, Dept. of Computer Science, Univ. of Amsterdam, Feb. 1993.

....trace of memory references may be constructed. This can be used for the evaluation of cache and TLB performance of microprocessor components in a heterogeneous architecture. 4. 2 Architecture simulation The Sesame architecture models are implemented in the discrete event simulation language Pearl [14]. This is a relatively small but powerful language Processor 1 Memory Memory Shared medium load(word) compute(word) load(word) compute(word) load(word) compute(word) In this example a block consists of three words, operations are interleaved. and in the real program High level ....

H. L. Muller. Simulating computer architectures. PhD thesis, Dept. of Computer Science, Univ. of Amsterdam, Feb. 1993.

....performing mixed level simulations. Currently, these issues are still largely open research problems. The architecture models in Sesame are implemented using a small but powerful discrete event simulation language, called Pearl, which provides easy construction of the models and fast simulation [15]. Evidently, these characteristics greatly improve the scope of the design space that can be explored in a reasonable amount of time. The architecture library components in Sesame are not meant to be fixed building blocks with pre defined interfaces but merely template models which can be freely ....

H.L. Muller. Simulating computer architectures. PhD thesis, Dept. of Computer Science, Univ. of Amsterdam, Feb. 1993.

....The second simulation trajectory in Artemis, provided by the Sesame framework, is a research effort from the University of Amsterdam in close collaboration with the Spade team. Instead of using TSS, the Sesame architecture models are implemented in the discrete event simulation language Pearl [24]. This is a relatively small but powerful object based language which has specifically been designed with the purpose of (abstract) computer architecture modeling in mind. As a consequence, Pearl has shown to be extremely suitable for easily and quickly building new or extending existing ....

H. L. Muller, Simulating computer architectures, Ph.D. thesis, Dept. of Comp. Sys, Univ. of Amsterdam, Feb. 1993.

....while there are enough free flitbuffers. In [4] McKinley and Trefftz describe a simulation algorithm that exploits the implicit movement of intermediate flits and that deals with the problem of multiple flitbuffers. Our network simulator, written in the architecture simulation language Pearl [6], has been implemented in both the naive manner (simulating every single flit) and using the optimized algorithm from [4] The first model was used to verify the more sophisticated implementation of the latter with small communication loads. The efficient simulation model showed an efficiency ....

H. L. Muller. Simulating computer architectures. PhD thesis, Dept. of Comp. Sys, Univ. of Amsterdam, Feb. 1993.

....successful usage [2, 3] On the other hand, Java offers an efficient and flexible simulation engine for DES with its complex control of the computational process. In general, simulation studies and experiments are pursued with specific simulation languages such as MODSIM III, SIMULA 67 or Pearl [7], or with general purpose languages such as C or Fortran that are extended with simulation libraries. Both approaches have their pros and cons. Simulation languages automatically provide most of the features needed in programming a simulation model, and by the design of the simulation language, it ....

....its aim to support an integral conceptual framework for discrete event modeling, while the simulation engine efficiently manages and executes the events in the simulation. In this article we will first describe the conceptual modeling framework for DES as used within the Pearl simulation language [7]. Next, we show how this framework is incorporated by a natural extension of the Java language. Here, we also discuss the aspects of the different levels of concurrency in the Java execution model, and the potential exploitation of concurrency by parallel and distributed execution of the ....

MULLER,H . Simulating Computer Architectures. PhD thesis, Department of Computer Science, University of Amsterdam, Amsterdam, The Netherlands, Feb. 1993.

....ENVIRONMENT The multi layered simulation environment of Mermaid is shown in Figure 1. The lowest level, referred to as the architecture level, contains the architecture simulation models. These models are implemented in a highly modular fashion using the object oriented simulation language Pearl [Muller, 1993], which allows flexible evaluation by means of parameterization. The simulators are driven by traces of abstract instructions, called operations, representing processor activity, memory I O and message passing communication. Simulating at the level of operations has several consequences. As the ....

Muller, H. L. 1993. Simulating computer architectures. PhD thesis, Comp. Sys. Dept., Univ. of Amsterdam (Feb.).

....n i are routed to mesh layer i. This non adaptive routing scheme is deadlock free because messages do not change of mesh layer during their journey. 3 Simulation methodology The wormhole network simulator used in this study has been implemented in the object oriented simulation language Pearl [7]. An example of the simulation model infrastructure is shown in Figure 3. It depicts the model of a four node cluster and contains all the basic components. These components, expressed in separate Pearl objects, consist of a processor, a Virtual Communication Processor (VCP) a channel (either ....

H. L. Muller. Simulating computer architectures. PhD thesis, Dept. of Comp. Sys, Univ. of Amsterdam, Feb. 1993.

....a certain duration. 4 Architecture modelling The architecture model accounting for computational behaviour involves a single node of the multicomputer, whereas communication behaviour is modelled by a multi node model. Both models are implemented in the object oriented simulation language Pearl [13]. This language was especially designed for easily and flexibly implementing simulation models of computer architectures. 4.1 Single node computational model The single node computational template model allows for simulating the processors and memory hierarchy of a MIMD node. It is generic in the ....

H. L. Muller. Simulating computer architectures. PhD thesis, Dept. of Comp. Sys, Univ. of Amsterdam, Feb. 1993.

....to layer i. This non adaptive routing scheme is deadlock free because messages do not switch from layer during their journey. 3 Simulation methodology The wormhole network simulator used in this study is trace driven and has been implemented in the object oriented simulation language Pearl [7]. An example of the simulation model infrastructure is shown in Figure 3. It depicts the model of a four node cluster and contains all the basic components. These components, expressed in separate Pearl objects, consist of a processor, a Virtual Communication Processor (VCP) a channel (either ....

H. L. Muller. Simulating computer architectures. PhD thesis, Dept. of Comp. Sys, Univ. of Amsterdam, Feb 1993.

.... copy defined thus: copy [ copy (x:xs) x:copy xs The difference is due to the fact that printing output in a functional program can be expensive: strings, and printed output in particular, are manufactured by appending program lines reference primitives short description event 84 [10] list, data Event driven simulation of a set reset fliflop. The state after 100000 transitions is calculated. wang 100 [24, 21] list, tuple, float Wang s algorithm for solving system of linear equations based on a tri diagonal 100 Theta 100 matrix. fft 130 [8] list, tuple, float, bit, complex, ....

H. L. Muller. Simulating computer architectures. PhD thesis, Dept. of Comp. Sys, Univ. of Amsterdam, Feb 1993.

....they include the notion of (virtual) time. Apart from procedure oriented (Andrews and Schneider 1983) general purpose languages like Simula (Dahl and Nygaard 1967) most formalisms are based on a message passing paradigm where models are more easily constructed to resemble the system under study (Muller 1993; Nichols and Edmark 1988) A mixed paradigm example is Csim (Schwetman 1986) 1 Although simulation, based on an imperative formalism inherently provides high accuracy, the typical trade off is evaluation (i.e. simulation) cost. This cost issue is even more prominent given the fact that ....

Muller, H. 1993. Simulating Computer Architectures.

.... thus fully capturing system dynamics (e.g. contention, data dependent control flow) Apart from procedure oriented [2] general purpose languages like Simula [4] most formalisms are based on a message passing paradigm in which models are more easily constructed to resemble the system under study [12] (a mixed paradigm example is Csim [16] Although accurate, simulation entails evaluation costs that are often prohibitive, in contrast to task graph reduction, which represents the opposite extreme in the accuracy cost trade off. We present a new, procedure oriented, performance modeling ....

H.L. Muller, Simulating Computer Architectures. PhD thesis, Department of Computer Systems, University of Amsterdam, Amsterdam, The Netherlands, 1993.

....HyperM. This suffices to give a correct simulation at the task level. In a hierarchical memory architecture, this level of detail is insufficient: bus contention and cache behaviour are paramount in determining the performance; the simulator used in Section 3. 5 is extensively described by Muller [Muller93b] 2.4 Summary For ideal multiprocessors (no memory inhomogeneity, no scheduler contention, no overhead costs for task creation or synchronisation etc. choice of any List Scheduling algorithm grants good performance; moreover, all List Scheduling algorithms have the same attainable wost case ....

....the scheduler should consider such inter task locality issues in its decisions; in fact, again we meet data communication costs as an extra parameter in scheduling. 3.5. 1 Experiments We set up an experiment with the bus level simulator of the Futurebus protocol described in [Muller92a] and [Muller93b] to investigate possible trade offs between processor load imbalance and inter task locality issues, using the benchmark described above (which now also comprised the parallel functional IDA implementation) The scheduling algorithms we implemented share one property: one of the children created ....

H. L. Muller. Simulating computer architectures. PhD thesis, Dept. of Comp. Sys, Univ. of Amsterdam, 1993.

....of computational and communication behaviour, two different architecture models of the MIMD platform are required. The architecture model for computation involves one single node of the MIMD platform, whereas communication is modelled by a multi node model. Both models, implemented in Pearl [Muller93] are generic in the sense that both the GCel and the PowerStone architectures can be represented by means of parameterization. The base computational architecture model consists of the MIMD node s processors, caches, bus and memory. These components are fully parameterized to be able to evaluate ....

H. L. Muller. Simulating computer architectures. PhD thesis, Dept. of Comp. Sys, Univ. of Amsterdam, 1993.

....specifically the statistical analysis engine of Pearl. Section 3 gives an overview of the structure of the GUI support library. A case study which shows how the GUI support library is used, is found in section 4, and finally, in section 5 is a summary of this paper is presented. 2 Pearl Pearl[7, 6] is an object oriented discrete event simulation language with method based communication primitives. In Pearl simulations, the objects represent modules within the computer architecture model, such as a processor, a memory, or a cache. 2.1 Objects and communication Objects in Pearl are ....

Henk Muller. Simulating Computer Architectures. PhD thesis, University of Amsterdam, 1993.

....which represent a specific trade off between analysis accuracy and cost. Approaches aimed for accuracy involve the use of probabilistic techniques based on queueing networks [10, 15] stochastic graphs [13, 18] timed Petri nets [1, 20] and stochastic process algebras [8] as well as simulation [16, 19]. Due to the exponential state space complexity associated with these models, however, the computational costs may easily prohibit frequent use of such techniques in a design loop. Although compile time techniques entail a sacrifice in accuracy when compared to the above approaches this loss may ....

H.L. Muller, Simulating Computer Architectures. PhD thesis, University of Amsterdam, 1993.

....31.9 0.6 typecheck 27679958 0.2 35065003 0.4 61.6 1.8 solid 11673355 9.4 32570915 14.1 91.5 15.0 complab 13749717 0.0 29405970 0.1 37.9 2. 1 Table 1: The result of the thunk lifting of the benchmark programs applications (wang [17, 16] fft [7] wave4 [16] and solid [1] The event [10] program embodies the core of a simulation program. The programs sched [16] and ida [2] implement search algorithms typically found in artificial intelligence applications. An image processing application is present in the form of complab [14] There are also programs that are parts of compilers ....

H. L. Muller. Simulating computer architectures. PhD thesis, Dept. of Comp. Sys, Univ. of Amsterdam, Feb 1993.

....locally and in the correct state before the operation is performed. As the transputer does not provide memory management, these references cannot be trapped by hardware so must be intercepted in software. To achieve this the code is annotated after the compilation stage (as in Tango [10] and MiG [11] ) After the compiler has generated transputer assembler, the assembly code is modified so that each non local read and write operation is replaced by a function call to the protocol handler. The protocol handler first tests if the trapped reference is indeed a shared access and then either ....

H. L. Muller. Simulating computer architectures. PhD thesis, Department of Computer Systems, University of Amsterdam, February 1993.

....scheduler. This certainly simplifies, but not trivializes, the process of parallelising Pearl. Before discussing parallel discrete event simulations, first a description of the simulation language Pearl will be given. Chapter 3 The simulation language Pearl The language Pearl 1 [Overeinder89, Muller93] is embedded in the simulation environment Oyster [Muller93] that should stimulate a computer architect to evaluate the performance of an architecture during an early stage of design. The design of Pearl has been greatly influenced by three other languages: POOL [America89] C [Kernighan78] and ....

....process of parallelising Pearl. Before discussing parallel discrete event simulations, first a description of the simulation language Pearl will be given. Chapter 3 The simulation language Pearl The language Pearl 1 [Overeinder89, Muller93] is embedded in the simulation environment Oyster [Muller93] that should stimulate a computer architect to evaluate the performance of an architecture during an early stage of design. The design of Pearl has been greatly influenced by three other languages: POOL [America89] C [Kernighan78] and SIMULA [Birtwistle73] A Pearl program consists of a ....

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H. L. Muller. Simulating computer architectures. PhD thesis, Dept. of Comp. Sys, Univ. of Amsterdam, 1993.

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Muller H. L.: Simulating Computer Architectures. PhD thesis, Dept. of Comp. Sys, Univ. of Amsterdam 1993

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H.L. Muller. Simulating computer architectures. PhD thesis, Dept. of Computer Science, Univ. of Amsterdam, Feb. 1993.

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H. L. Muller. Simulating Computer Architectures. PhD thesis, Department of Computer Systems, University of Amsterdam, Netherlands, February 1993.

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H.L. Muller, Simulating Computer Architectures. PhD thesis, Department of Computer Systems, University of Amsterdam, Amsterdam, The Netherlands, 1993.

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