Advanced Micro Devices, Inc. AM29050 Microprocessor User's Manual, 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....Hardware Platform. b) Structure of the Configuration Compiler. for the hardware platform, and the hardware platform which ultimately executes the program. 2. 1 Hardware Platform The hardware platform, shown in Figure 1a, consists of (i) a core processor, namely the AMD AM29050 RISC processor [22], and (ii) a reconfigurable platform that consists of a set of FPGAs that are interconnected to the core processor through the latter s coprocessor interface. Details of the hardware platform can be found in [23] 2.2 The Configuration Compiler The configuration compiler accepts a user program ....

Advanced Micro Devices, Inc. AM29050 Microprocessor User's Manual, 1991.

....architecture will allow an operation to span 3 FPGAs thus allowing larger operations to be synthesized by partitioning the data flow graph. To provide a balance between hardware and software performance we chose a fast RISC processor to complement the adaptive elements. The AMD Am29050 processor [15] clocked at 33MHz can provide about 28 MIPS performance. In addition, the processor has a built in floating point unit. Since our synthesis does not support floating point operations, it was important that the host processor have this capability. Figure 8 shows the system level architecture of ....

Advanced Micro Devices, Inc. AM29050 Microprocessor User's Manual, 1991.

....Figure 6: Interconnect structure for a multiple FPGA design. reconfigurable resource as shown in Figure 6. Each XC4010 connects through buffers to both the address and data buses of the Am29050. The Am29050 coprocessor interface allows 64 bit writes in a single cycle with a single instruction [16]. The coprocessor interface writes data on the address bus in addition to the data on the data bus. The coprocessor interface is utilized to transfer data to the XC4010s in 60ns. There is one wait state for writes to the XC4010s and static RAM and two wait states for reads. Thirty two bits may be ....

Advanced Micro Devices Inc, Sunnyvale, California, Am29050 Microprocessor User's Manual, 1990. 31 Draft

....paradigm of hardware software codesign used in the Armstrong III PRISM II system [12] 13] Armstrong III is a loosely coupled MIMD multicomputer composed of several PRISM II boards, each connected to its own communications board. Each PRISM II board includes a 33 MHz AMD Am29050 RISC processor [68] for conventional processing and three Xilinx XC4010 FPGAs [16] for reconfigurable computing. Ideally, the user need only write a C or C implementation of a system, run the PRISM II configuration compiler to map the software bottlenecks to hardware once they ve been identified, and compile the ....

Advanced Micro Devices, AM29050 Microprocessor User's Manual, 1991, http://www.amd.com/.

....performance results will be examined. Chapter 2 Hardware Architecture 2.1 Overview Each node of Armstrong III is divided into a processor board and a communication board. The processor board, similar to a workstation, performs the actual computations and is based on the AMD 29050 RISC processor [8]. The communication board, similar in function to a router, contains 40 megabit serial links and manages communication between nodes in the parallel processor. The processor and communication boards are connected by a custom parallel bus through a 96 pin Eurocard connector. Nodes have no direct ....

....Figure 2.1: Armstrong III Multiprocessor 2.2 Processor Board The Am29050 is a single cycle per instruction, 32 bit RISC processor running at 33MHz. The Am29050 has an integral, multi stage, pipelined floating point unit that is rated at a peak 33 million floating point operations per second [8]. The Am29050 has 192 general purpose registers and hardware support for multiply, multiply accumulate and square root operations. The processor board can support up to 32 megabytes of DRAM through the use of the V29BMC 1 burst memory controller [9] The V29BMC takes advantage of some dynamic ....

Advanced Micro Devices. Am29050 Microprocessor User's Manual, 1991.

.... simulation, hardware monitoring, kernel based simulation 1 INTRODUCTION Many computers support virtual memory by providing hardware managed translation lookaside buffers (TLBs) However, beginning with the ZS 1 in 1988 [23] an increasing number of computer architectures, including the AMD 29050 [4], the HP PA [12] and the MIPS RISC [13] have shifted TLB management responsibility into the operating system. These software managed TLBs simplify hardware design and provide greater flexibility in page table structure, but typically have slower refill times than hardware managed TLBs [11] At ....

American Micro Devices, Inc., Am29050 Microprocessor User's Manual, Sunnyvale, CA, 1991.

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