J. M. Daveau, G. F. Marchioro, T. Ben Ismail, A. A. Jerraya, "Protocol Selection and Interface Generation for HW-SW Codesign", IEEE Transactions on VLSI Systems, Vol. 5, No. 1, pp. 136-144, March 1997.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....has not been considered. Furthermore, hardware software co design methodologies that synthesize the hardware component as an ASIC, pay little attention towards optimizing the memory mapping since the amount of logic that can be mapped to an ASIC is less severely constrained than that for FPGAs [2, 7, 8]. Most previous work on memory mapping and allocation of multiport memories has been done in the context of data path synthesis and has focused on purely data flow designs (no control constructs) 9, 10, 11] These algorithms do not deal with unknown data access patterns because no control flow ....

J. Daveau, G.F. Marchioro, T. Ben-Ismail, and A.A. Jerraya. Protocol selection and interface generation for hw-sw codesign. IEEE Transactions on VLSI Systems, March 1997.

....of bus configuration is given in Section 9. Section 10 extends the approach mentioned above to enlarge the explored design space. Experimental result is described in section 11. Finally, section 12 gives the conclusion. 2. Related Work Much research has been done for communication synthesis. In [3], Daveau deals with both bus protocol selection and interface generation and is based on binding allocation of communication units. In [11] Yen crate a new processing element and a bus when it is not possible to assign a process to an already existing processing elements or a communication on a ....

Jean-Marc Daveau, Gilberto Fernandes Marchioro, Tarek Ben-Ismail, and Ahmed Amine Jerraya. Protocol selection and interface generation for hw-sw codesign. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pages 136--144, March 1997.

....Asynchronous, Locally Synchronous Design Style , Accepted for publication in DAC 99. Other papers [26] T. Lazraq, F. stman, J. berg, H. Tenhunen, ATM Switching System Performance Analysis via Modelling and Simulation , In Proc. of SIMS 94 Conference, pp 326 332, Stockholm, Aug. 17 19, 1994. [27] T. Lazraq, J. berg, H. Tenhunen, FPGA Basic ATM Traffic Shaper for Event Building Networks , In Proc of the 8th Annual IEEE International ASIC Conference and Exhibit (ASIC 95) pp 177 180, Austin, Texas, Sept. 18 22, 1995. 28] J. T.A. Waldemark, T. Lindblad, C. S. Lindsey, K. E. Waldemark, J. ....

....SOLAR. The system is then partitioned into DesignUnits that implements the behaviour and ChannelUnits that implements the communication. The channel behaviour is selected from a library of protocols. The selection of the communication protocol is treated as an allocation problem by Daveau et al. [30, 27]. Function calls representing communicating primitives of the selected protocol is then inserted into the DesignUnits. The advantage with the method is its clean separation of communication from behaviour. A method arguing against the use of protocol libraries for selecting of an appropriate ....

J.-M, Daveau, G.F. Marchioro, T.B. Ismail, A.A. Jerraya, "Protocol Selection and Interface Generation for HW-SW Codesign", In Transactions on VLSI Systems, Vol. 5, No. 1, pp. 136-144, March, 1997.

....The communication semantics are based on the concept of remote procedure call communication via send receive operations, similar to CoWare. Types of protocols supported include blocking and non blocking communication. A channel is implemented by allocating communication units from a library [7]. These library units are composed to fulfil a set of constraints put on the channel. The library consists of a set of communication services and protocols along with their implementations (a mixture of hardware and software) Interface synthesis techniques are used to permit communication between ....

J-M Daveau, G. F. Marchioro, T. Ben-Ismail, and A. A. Jerraya, Protocol selection and interface generation for hw-sw codesign, IEEE Transaction on Very Large Scale Integration, Vol. 5, No. 1, pp. 136--144, 1997.

....Vahid and Tauro[18] and Ernst and Benner [5] both proposed using a communication library with a standard API (Application Program Interface) However, protocols based on message priorities require a unique allocation of all the priorities on the bus in addition to providing an API. Daveau et al. [4] take a behavioral description and automatically select a protocol from a library to implement the communication. They use nonstandard low level protocols such as bidirectional handshake and dual fifo. Gajski et al. 6] consider all of the events on the bus, but they implement a simple low level ....

J-M. Daveau, G.F. Marchioro, T.Ben-Ismail, and A.A. Jerraya. Protocol selection and interface generation for hw-sw codesign. IEEE Trans. on Very Large Scale Integration (5)1:136-144, March 1997.

....Complex systems are naturally modelled as communicating concurrent processes. Refining these abstract communications to intra and inter component (ASICs, processor cores, memories etc. communication primitives is a major part of the design effort and is now being treated as a research problem [7, 8]. Furthermore, languages and notations that were not main stream in the hardware design community, are being explored to specify communication dominated functionality [9, 10] The structural and physical domains of the Y chart are merged into this domain because movement from a topological to a ....

J.-M. Daveau, G.F. Marchioro, T. Ben-Ismail, and A.A. Jerraya, "Protocol Selection and Interface Generation for HW-SW Codesign ", IEEE Transactions on VSLI Systems, vol. 5, no. 1, pp. 136 - 144, March 1997.

No context found.

J.M. Daveau, G.Marchioro, T. Ben-Ismail and A.A. Jerraya, "Protocol Selection and Interface Generation for Hw-Sw codesign", IEEE Trans. on VLSI Systems, vol. 5, no.1, pp.136-144, 1997.

No context found.

J-M. Daveau, G. F. Marchioro, T. Ben-Ismail, and A. A. Jerraya, "Protocol Selection and Interface Generation for HW-SW Codesign", IEEE Transactions on VLSI Systems, vol. 5, no. 1, pp. 136--144, Mar. 1997.

No context found.

J.M. Daveau, G. Marchioro, T. Ben-Ismail and A.A. Jerraya, "Protocol Selection and Interface Generation for Hw-Sw codesign", IEEE Trans. on VLSI Systems, vol. 5, no.1, pp.136-144, 1997.

....in a modular way. The module interfaces and communication channels can be refined separately from the refinement of module behavior. Together with recently introduced high abstraction levels of communication (e.g. Functional Interface (FI) 6] Remote Procedural Call (RPC) Abstract) Channels [12][4], and Virtual Component Interface (VCI) 6] etc. the separation enables gradual communication refinement. In gradual communication refinement, system communication can be refined from a high abstraction level (e.g. FI or RPC) to a low level (e.g. VCI or cycle accurate models) separately from ....

....Refining communication protocols is one of crucial tasks in system design since they can have significant impact on system runtime, power consumption and resource usage. Related to the refinement, there is a huge design space with candidate communication protocol types (FIFO, handshake, etc) [4], protocol specific parameters (FIFO size, blocking or non blocking read write, etc) 2] and different implementation styles of module interface behavior [7] 8] Thus, for extensive design space exploration, fine granularity is very important in gradual communication refinement. To achieve ....

[Article contains additional citation context not shown here]

J.-M. Daveau, G. F. Marchioro, T. Ben-Ismail, and A. A. Jerraya. Protocol Selection and Interface Generation for HW-SW Codesign. IEEE Transactions on VLSI Systems, 5(1):136--144, Mar. 1997.

....model described in VHDL from the SDL module. The SDL model is composed of a set of concurrent high level processes communicating through message passing and synchronized through infinite queue. This model is refined into an implementation composed of VHDL blocs communicating through signals [4]. Abstract heterogenous chanel realization Additional component Subsystem IP Matlab Control unit protocol adaptor Connector SPEED SDL subsystem . Interlanguage communication synthesis During this step the abstract communication channels are mapped on explicit communication protocol. ....

....component Subsystem IP Matlab Control unit protocol adaptor Connector SPEED SDL subsystem . Interlanguage communication synthesis During this step the abstract communication channels are mapped on explicit communication protocol. The communication synthesis is realized in two main stages [4]: The first stage is the protocol choice and allocation. The communication protocols are specified in a communication library. The allocation stage determines if the protocol chosen to realize the abstract channel respects the requirements of this channel. The second stage is the interface ....

J.M.Daveau, G. Marchioro, T. Ben-Ismail, and A.A.Jerraya "Protocol Selection and Interface Generation for Hw-Sw Codesign", IEEE Trans. on VLSI Systems, vol.5, no.1, 1997, pp. 136-144.

....for an arbitrary bus topology specified by the system architect. The synthesis processes make a map of high level functions to the computational components of a particular architecture. An application specific real time operating system is generated for each processor in the system. Daveau [18] takes a behavioral description and automatically selects a protocol from a library to implement the communication. But, this approach solved only the problem for homogeneous systems. This paper extends the work of Daveau [18] to handle interlanguage communication. The main advantages of our ....

....operating system is generated for each processor in the system. Daveau [18] takes a behavioral description and automatically selects a protocol from a library to implement the communication. But, this approach solved only the problem for homogeneous systems. This paper extends the work of Daveau [18] to handle interlanguage communication. The main advantages of our approach are: communication interface synthesis of multilanguage specifications, a complete communication synthesis approach: network synthesis and protocol selection, interface synthesis and adaptation modules for ....

[Article contains additional citation context not shown here]

J.M. Daveau, G.Marchioro, T. Ben-Ismail and A.A. Jerraya, "Protocol Selection and Interface Generation for Hw-Sw codesign", IEEE Trans. on VLSI Systems, vol. 5, no.1, pp.136-144, 1997.

....focuses on the methodological aspect from the designer s point of view and not on the algorithms and techniques used in Cosmos. Most of the details of the intermediate model Solar and the behavioral transformation primitives are detailed in [4] the communication synthesis methods are explained in [9] and the code generation (C VHDL ) techniques can be found in [26] However for a improved clarity of the paper we will introduce the models and techniques used when needed. The rest of this paper details this partitioning scheme and illustrates its efficiency through an example. Section II deals ....

J. M. Daveau, T. Ben-Ismail, G. F. Marchioro, A. A. Jerraya, Protocol Selection and Interface Generation for HW-SW Codesign, IEEE Transactions on VLSI Systems, Special issue on Design Automation of complex integrated systems, September 1996.

No context found.

J. M. Daveau, G. F. Marchioro, T. Ben Ismail, A. A. Jerraya, "Protocol Selection and Interface Generation for HW-SW Codesign", IEEE Transactions on VLSI Systems, Vol. 5, No. 1, pp. 136-144, March 1997.

No context found.

J. M. Daveau, G. F. Marchioro, T. Ben Ismail, A. A. Jerraya, "Protocol Selection and Interface Generation for HW-SW Codesign", IEEE Trans. on VLSI Systems, Vol. 5, No. 1, pp. 136-144, March 1997.

No context found.

J. M. Daveau, G. F. Marchioro, T. Ben Ismail, A. A. Jerraya, "Protocol Selection and Interface Generation for HW-SW Codesign", IEEE Trans. on VLSI Systems, Vol. 5, No. 1, pp. 136-144, March 1997.

No context found.

J. Daveau, G. F. Marchioro, T. Ben-Ismail, A. A Jerraya, "Protocol selection and interface generation for HWSW codesign", In IEEE Trans. on VLSI Systems, Vol. 5, No. 1, March 1997

No context found.

J. M. Daveau, G. F. Marchioro, T. Ben-Ismail, and A. A. Jerraya. Protocol selection and interface generation for hw-sw codesign. IEEE Tr. on VLSI Systems, 5(1):136--144, March 1997.

No context found.

J. Daveau et al. Protocol selection and interface generation for HW-SW Codesign. IEEE TVLSI, March 1997.

No context found.

J. Daveau, G.F. Marchioro, T. Ben-Ismail, and A.A. Jerraya. Protocol selection and interface generation for HW-SW Codesign. IEEE TVLSI, March 1997.

No context found.

DAVEAU,J.-M.,MARCHIORO,G.F.,BEN-ISMAIL,T.,AND JERRAYA,A.A. Protocol selection and interface generation for hw-sw codesign. IEEE Transactions on VLSI Systems 5, 1 (March 1997), 136--144.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC