F. Sanchez and J. Cortadella. Reducing register pressure in software pipelining. J. Inf. Sci. & Eng., 14:265--279, 1998. Home/Search Document Details and Download
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Combining Extended Retiming and Unfolding for Rate-Optimal.. - O'Neil, Sha (1999) (Correct)
....the DFG G remains the same, but the length of the longest zero delay path (the clock period of G, denoted cl(G) is decreased. This technique was introduced in [10] to optimize the throughput of synchronous circuits, and has since been used extensively in such diverse areas as software pipelining [1,16] and hardware software codesign [6,17] We have shown previously that this traditional form of retiming [12] cannot produce optimal results when applied individually. The same is true for unfolding (as we will see) but the combination of traditional retiming and unfolding will achieve optimality ....
F. Sanchez and J. Cortadella. Reducing register pressure in software pipelining. J. Inf. Sci. & Eng., 14:265--279, 1998.
Reducing Register Pressure in Software Pipelining - Sánchez, Cortadella (1997) (1 citation) Self-citation (S'anchez Cortadella) (Correct)
....DDG. On the other hand, for a given dependence e = u; v) ffi(e) 0 if e is an ILD and ffi(e) j Gamma i if e represents an LCD between u i and v j . A dependence (u; v) will be depicted as u (u) ffi(u;v) Gamma v (v) Therefore, u i d v i and u i v i d represent the same dependence [7]. We will use u ffi(u;v) Gamma v to denote a dependence in which (u) v) Thus, for the sake of simplicity, an ILD (u; v) will be depicted as u v. An instruction may represent a single operation or a group of them. For the sake of simplicity, henceforth instructions and operations will ....
....will be depicted as u v. An instruction may represent a single operation or a group of them. For the sake of simplicity, henceforth instructions and operations will be equivalent. However, the approach proposed in this paper may work with different models of superscalar and VLIW machines (see [7] for details) We will call result latency of u the number of cycles required by u to produce a result, and issue latency of u the minimum number of cycles required between the issuing of two instructions of type u to the same functional unit (FU) As an example of loop representation. Figure 1(a) ....
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F. S'anchez and J. Cortadella. Reducing register pressure in software pipelining. Technical Report UPCDAC -1997/74, UPC-DAC, November 1997. Available at www.ac.upc.es/homes/fermin.
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