| J.J.Joyce, "Formal specification and verification of microprocessor systems", Integration, the VLSI Journal, 7:247-266, September 1989. |
....on different abstraction levels. However they have the restriction that ordering of specification and implementation in terms of indexed signals and number of loops, must be the same in order to proof equivalence. Other techniques involve the use of theorem provers or proof assistants. In [9] and [10] the correctness of a single microprocessor is proven. However during all these proofs a lot of user interaction knowledge was necessary during the proofs. In the array synthesis community, some effort on correctness checking is performed but oriented to restricted models [11] This works well for ....
J.J Joyce. "Formal Specification and Verification of Microprocessor Systems". Integration, the VLSI Journal, 7:247--266, September 1989.
....techniques based on recursion are mainly present in theorem provers and proof assistants. They are capable of verification at a high abstraction level, but they require much manual assistance and are oriented to local modifications (e.g. Lambda [5] The same problem is encountered in methods like [8] and its recent followers, where the correctness of (micro)processors is proven. On the other hand, dataflow based methods start from the assumption that the control flow (especially loop related) ordering of operations in the specification is not changed during the synthesis [6, 18] This is not ....
J.J.Joyce, Formal specification and verification of microprocessor systems, Integration, the VLSI Journal, Vol.7, pp.247-266, Sep. 1989.
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J.J.Joyce, "Formal specification and verification of microprocessor systems", Integration, the VLSI Journal, 7:247-266, September 1989.
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