R. A. Iannucci. Toward a dataflow/von Neumann hybrid architecture. In 15th Annual International Symposium on Computer Architecture, pages 131--140, June 1988.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....the current token s data dependencies. The multi thousand element associative structure required to do this search is not implementable even after twenty years of process scaling. Another flaw of the early Dataflow machines is that every token represents a high overhead synchronization event. Ian88] points out that von Neumann architectures also perform a synchronization event between each instruction, but the method of synchronization is very light weight: IP = IP 1 or IP = branch target. This allows von Neumann architectures to grind through straightline code very quickly. Fortunately ....

Robert Iannucci. Toward a dataflow/von Neumann hybrid architecture. In Proceedings Annual International Symposium on Computer Architecture, Honolulu, Hawaii, May 1988.

....latency seen by the processors. Relaxed memory consistency models [1, 5, 8] hide latency by allowing buffering and pipelining of memory references. Prefetching techniques [11, 16, 21, 23] hide the latency by bringing data close to the processor before it is actually needed. Multiple contexts [3, 12, 13, 26, 29] allow a processor to hide latency by switching from one context to another when a high latency operation is encountered. Our primary objective in this paper is to characterize the benefits and costs of these four latency hiding techniques in a systematic and consistent manner. Although one can ....

....contexts, is that it can be implemented using existing commercial processors, as has been done in DASH [18] 6 Multiple Context Processors Although prefetching is useful for many applications, it requires explicit programmer or compiler intervention. Processors with multiple hardware contexts [3, 12, 13, 26, 29] do not have this disadvantage. They make use of increased concurrency to hide latency. Each processor has several processes assigned to it, which are kept as hardware contexts. When the context that is currently running encounters a long latency operation, it is switched out and another context ....

R. A. Iannucci. Toward a dataflow/von Neumann hybrid architecture. In Proc. Int. Symp. Comput. Arch., pages 131 140, June 1988.

....(similar to grain sizes) for data flow programs. They analyze the problem, and an optimal mean resolution size is found. However an arbitrary algorithm for dividing the program, into grains of this size, is used. A similar approach has been taken by several compilers for non strict languages [14, 27, 28, 21]. In these languages, in general, data dependencies cannot be determined during compilation time. The main difficulty is therefore to avoid deadlock which may result if the grains are not carefully chosen. In early works, the assumption that larger grains are always better has been taken. ....

....in the EM 4 [22] tries to save time by trying to schedule non ready grains if the execution unit is idle. If the last missing operand arrives in the next cycle, this pre fetching technique saves time. This does not comply with our strict model of scheduling only ready grains. Iannucci [14] describes another hybrid architecture where Von Neumann processors are enhanced with a fast context switch mechanism for switching between grains. The processors are connected through some communication network. Unlike our model, the running of a grain can be suspended and rescheduled with almost ....

R.A. Iannucci. Towards a data flow Von Neumann hybrid architecture. In International Symposium on Computer Architecture, pages 131--140, 1988.

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R. A. Iannucci. Toward a dataflow/von Neumann hybrid architecture. In 15th Annual International Symposium on Computer Architecture, pages 131--140, June 1988.

No context found.

R.A. Iannucci. Toward a dataflow/von neumann hybrid architecture. In Proceedings of the Fifteenth International Symposium on Computer Architecture, 1988.

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R.A. Iannucci. "Toward a dataflow/von Neumann hybrid architecture", Proc. of 15th symposium on Computer Architecture (ISCA-15), pp 131-140, 1990.

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