P. W. Foulk, "Data-folding in SRAM configurable FPGAs", in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, D. A. Buell and K. L. Pocek, Eds., Napa, CA, Apr. 1993, pp. 163--171.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....that is being updated, without interruption to the rest of the system on chip. This type of reconfiguration is referred to as dynamic reconfiguration (or run time reconfiguration) and has been actively researched for the last decade. Although several interesting applications have been reported [4 11], it appears that no generic class of circuits that would benefit from dynamic reconfiguration has been identified. We focus on a class of circuits that we refer to as programmable, multi function cores (PMCs) This is a broad category of circuits that includes devices such as UARTs, PCI ....

P. W. Foulk, "Data-folding in SRAM Configurable FPGAs", in IEEE Symposium on Field Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (Eds.), pp 163 - 171, Los Alamitos, California, April 1993

....is used to parameterise the source and server mean rates, the queue length, and random seeding of linear feedback shift registers (LFSR) after the basic simulator circuits have been configured on the FPGA. An example of a similar technique, referred to as data folding, has been described by Foulk [8]. The two AT6005 devices and a FIFO memory were prototyped on an ISA (Industry Standard Association interface) card for an IBM PC. The FPGAs are programmed by the host PC which also controls execution of the simulation model and retrieves simulation results from the simulator via the FIFO memory. ....

P. Foulk, I. Hodson, Data Folding in SRAM Configurable FPGAs, Ed. D. Buell and K. Pocek, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, Napa, Ca., 1993

....circuitry. This type of reconfiguration is called dynamic reconfiguration (or run time reconfiguration) 1] Dynamic reconfiguration of FPGAs has been actively researched for the last decade. During this time, several interesting applications of dynamic reconfiguration have been reported [2 9]. Despite this progress, we are not aware of any research that has identified a generic class of circuits that would benefit from being dynamically reconfigured. Our research shows that programmable IP cores are such a generic class. The following section details a VHDL coding methodology for ....

P. W. Foulk, "Data-folding in SRAM Configurable FPGAs", in IEEE Symposium on Field Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (Eds.), pp. 163 - 171, Los Alamitos, California, April 1993

....Furthermore, the results indicate the potential for reducing the power consumption of the circuits. 1. Introduction Dynamic reconfiguration of FPGAs has been actively researched for the last decade. During this time several interesting applications of dynamic reconfiguration have been reported [1 8]. Despite this progress, the identification of generic classes of circuits that would benefit from being dynamically reconfigured remains a key, open problem. This paper reports on an investigation to establish a class of circuits whose performance can be improved by the use of dynamic ....

P. W. Foulk, "Data-folding in SRAM Configurable FPGAs", in IEEE Symposium on Field Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (Eds.), pp 163 - 171, Los Alamitos, California, April 1993

....for interactive development. The second device is a Xilinx XC6216 FPGA and is the target for the dynamically reconfigurable application. The application implements a pattern matching algorithm, which requires intratask reconfiguration. The algorithm is based on a concept known as data folding [6] or more recently known as run time constant propagation [7] The principle of data folding is quite simple: fixed coefficient implementations of circuits such as pattern matchers or multiplication units execute more quickly, in a smaller area, than the equivalent variable coefficient ....

P. W. Foulk & L.D. Hodson, Data Folding in SRAM Configurable FPGAs, IEEE Workshop on FPGAs for Custom Computing Machines, pp. 163-171, Napa, CA, Apr. 1993

....partially evaluating the design according to the activation sequence. Inputs having a fixed value throughout a configuration can be used to simplify the hardware for that configuration# this process involves propagating the constant values through the circuit, and is sometimes called data folding [5]. Partial evaluation is usually carried out at compile time, and the resulting netlists are compiled by FPGA vendor tools (Figure 2) Partial evaluation can also take place at run time if the overheads involved can be tolerated [30] The fourth step, incremental configuration calculation, ....

....worst case occurs when n =2 m ; 1, the worst case can be improved by reconfiguring an additional cell to maximise wildcarding. 7.2 Pattern Matcher Example Our second example is a 64 bit pattern matcher. The structure of the reconfigurable version of our pattern matcher is shown in Figure 6 [5]# this design takes up 64 Theta 2 = 128 FPGA cells, whereas a design including an additional shift register for storing the pattern and an additional row of comparators will be twice as large. The test for the worst case configuration time is performed bychanging the pattern matcher 9 0 5 10 ....

FOULK, P.W.: `Data-Folding in SRAM Configurable FPGAs', IEEE Symposium on FPGAs for Custom Computing Machines, IEEE Computer Society Press, 1993, pp. 163--171.

....within a complex image processing system [47, 17] In addition, several development tools allow the specification of custom numerical data types within a system description. 14 Constant Propagation Another way of specializing a functional unit is to propagate or fold a constant into the circuit [51]. If an operand of a functional unit does not change during the course of a computation, significant hardware resources can be recovered by propagating the constant within the function. The registers and decoding circuitry used to hold the operand value can be removed. In addition, a constant ....

.... to free hardware for additional functionality [52, 53, 54] One such dedicated IIR filter has been shown to fit in half the space of its generalpurpose counterpart [55] Other application areas demonstrating this technique within FPGAs include neural networks [56, 57] and text searching [51, 58, 59]. 2.2.2 Exploitation of Concurrency Another advantage of application specific architectures is their ability to exploit concurrency. The exploitation of concurrency has been shown to reduce the overall cost of a computation within VLSI architectures [60] Many computationally intensive problems ....

P. W. Foulk. Data-folding in SRAM configurable FPGAs. In D. A. Buell and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 163--171, Napa, CA, April 1993.

....the conditions under which they will be loaded onto or removed from the FPGA. This is not always intuitive, especially when designs contain a large number of reconfigurable elements or have complex scheduling conditions. An example of such a dynamically reconfigurable application is data folding[3] or circuit parameterisation. Parameterisation of digital systems, whether implemented in software or hardware, is a commonly used technique. In software, a module that will be re used many times is written once in the form of a procedure or function. The module is designed to transform the data ....

P. Foulk, I. Hodson, Data Folding in SRAM Configurable FPGAs, In: D. Buell and K. Pocek (eds.), Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, Napa, Ca., 1993.

....propagate the search signal in less than 30 nanoseconds. The time taken for array initialisation and readback were not reported but Kean indicated that the software overhead associated with accessing the development board from the host computer took longer than the worst case search time. Foulk [9] described a dynamically reconfigurable pattern matcher for textbase searching that also used Algotronix FPGAs. His original design used registers in sliding window recognizers to hold the patterns that were being searched for in the textbase. He subsequently replaced the registers with dedicated ....

P. Foulk, I. Hodson, "Data Folding in SRAM Configurable FPGAs", In: D. Buell and K. Pocek (eds.), Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, Napa, Ca., pp 163-171, 1993.

....partially evaluating the design according to the activation sequence. Inputs having a fixed value throughout a configuration can be used to simplify the hardware for that configuration; this process involves propagating the constant values through the circuit, and is sometimes called data folding [4]. Partial evaluation is usually carried out at compile time, and the resulting netlists are compiled by FPGA vendor tools (Figure 2) Partial evaluation can also take place at run time if the overheads involved can be tolerated; it is likely that a design description more efficient than EDIF will ....

....for reconfiguring from one regular structure to another. The use of wildcarding for irregular configuration will be considered next. 7.2 Pattern Matcher Example Our second example is a 64 bit pattern matcher. The structure of the reconfigurable version of our pattern matcher is shown in Figure 6 [4]; this design takes up 64 Theta 2 = 128 FPGA cells, whereas a design including an additional shift register for storing the pattern and an additional row of comparators will be twice as large. In the reconfigurable pattern matcher, the pattern to match is determined by a gate that is selected by ....

P.W. Foulk, "Data-Folding in SRAM Configurable FPGAs", Proc. FCCM93, D.A. Buell and K.L. Pocek (eds.), IEEE Computer Society Press, 1993, pp. 163--171.

....that use a single fixed value for one of its inputs. Digital filters, for example, commonly use constant coefficients for the multiplier of each filter tap. The circuit resources required to build such constant operators can be reduced by folding the fixed operand value into the circuit [1]. Registers and decoding circuitry used to hold the operand value can be removed. In addition, standard logic optimization and minimization techniques can be used to further reduce the hardware [2] Several CCM applications have used this technique to reduce hardware and improve circuit speed. ....

.... into multipliers to free hardware for additional functionality [3, 4, 5] One such dedicated IIR filter has been shown to fit in half the space of its general purpose counterpart [6] Other application areas demonstrating this technique on FPGAs include neural networks [7, 8] and text searching [1, 9, 10]. 1.2 Run Time Constant Propagation If an operator within a system must support any arbitrary input value, special purpose constant propagated operators cannot be used and the advantages of constant propagation are not available. With dynamically configurable hardware, however, arbitrary input ....

P. W. Foulk. Data-folding in SRAM configurable FPGAs. In D. A. Buell and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 163--171, Napa, CA, April 1993.

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P. W. Foulk, "Data-folding in SRAM configurable FPGAs", in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, D. A. Buell and K. L. Pocek, Eds., Napa, CA, Apr. 1993, pp. 163--171.

No context found.

P. W. Foulk. Data-folding in SRAM configurable FPGAs. In D. A. Buell and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 163--171, Napa, CA, Apr. 1993.

No context found.

Patrick W. Foulk. `Data-folding in SRAM configurable FPGAs', in IEEE Workshop on FPGAs for Custom Computing Machines, Napa, California, April 1993, pp:163-171.

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