E. L. Lawler, "An approach to multilevel Boolean minimization," J. ACM, vol. 11, no. 3, pp. 283--295, 1964. Home/Search Document Not in Database Summary Related Articles Check |
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Rectangle Replacement and Variable Ordering: Two Techniques for .. - Søe (1994) (Correct)
....law the negation of a factored form is easily obtained and is itself a factored form. The literature has reported several attempts to minimize factored forms, see [BHS90] for a list of references, but unlike sum of products form it is hard to determine if a given factored form is optimal. Lawler [Law64] presented an algorithm for obtaining optimal factored forms, but the approach is only feasible for low complexity functions of few inputs [Wan89] 2.3 Binary decision diagrams Binary decision diagrams offer an alternative way of representing and manipulating Boolean expressions [Bry86] They ....
Eugene L. Lawler. An approach to multilevel Boolean minimization. Journal of the Association for Computing Machinery, 11(3):283--295, July 1964.
Exact Circuit Synthesis - Drechsler, Günther (1998) (3 citations) (Correct)
.... synthesis approaches for circuit design have been proposed in the past for two level and multi level synthesis [1, 7, 8, 6] While for two level realizations powerful tools for exact minimization have been developed [2] exact multi level optimization has only been considered in the 1960s [4, 3]. But these approaches were of limited practical interest, since they were only applicable to very small functions. However, meanwhile the computational power of modern workstations and the knowledge in efficient data structures has extremely increased. For this reason, exact circuit synthesis ....
E.L. Lawler. An approach to multilevel boolean minimization. Journal of the ACM, 11:283--295, 1964.
Spatial Entropy - A Unified Attribute to Model Dynamic.. - Rajgopal (1992) (Correct)
....the next section. 1.2 Motivation Why is such an attribute needed Almost all problems in CAD are NPcomplete [LP88] It is computationally intractable to find an exact optimal solution for all but the smallest problems. The problem of two level and multi level logical minimization is NP complete [BHMSV84, Law64]. Placement and layout tools face an NP complete problem in trying to embed a non planar graph on a plane with minimum arc crossing [GJ79] Complete gate level or transistor level simulation over all the input assignments takes exponential time. The best known deterministic algorithm to arrive at ....
.... function, it can be minimized (for literal count) using logic minimizers like espresso [BHMSV84] along with one of the minimization scripts in the UC, Berkeley MISII SIS (Sequential Interactive System) system [BRSVW87] But since exact multi level logic minimization requires exponential time [Law64], most minimizers use heuristics to find near optimal solutions. The optimality of such a solution is usually measured with respect to the minimal literal count in the multi level implementation. The number of literals influences the number of nodes in the implementation. Since spatial entropy ....
E. J. Lawler. An Approach to Multilevel Boolean Minimization. Journal of the ACM, pages 283--295, 1964.
Creating Hard Problem Instances In Logic Synthesis Using.. - Günther, Drechsler (1999) (Correct)
....important steps in the design process of ICs. Many heuristic synthesis approaches for circuit design have been proposed in the past. While for two level realizations powerful tools for exact minimization have been developed [4] exact multi level optimization has been considered only in the 1960s [8, 5]. But these approaches were of limited practical interest since they were only applicable to very small functions. However, meanwhile the computational power of modern workstations and the knowledge of efficient data structures has extremely increased. Therefore exact circuit synthesis becomes an ....
E.L. Lawler. An approach to multilevel boolean minimization. Journal of the ACM, 11:283--295, 1964.
A Fast Algorithm for OR-AND-OR Synthesis - Debnath, Vranesic (2003) (Correct)
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E. L. Lawler, "An approach to multilevel Boolean minimization," J. ACM, vol. 11, no. 3, pp. 283--295, 1964.
Cyclic Combinational Circuits - Riedel (2004) (Correct)
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E. L. Lawler, "An Approach to Multilevel Boolean Minimization," Journal of the ACM, Vol. 11, No. 3, pp. 283--295, 1964. 110
Synthesis of Reversible Logic Circuits - Vivek Shende Aditya (2003) (Correct)
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E. Lawler, "An approach to multilevel Boolean minimization," J. Assoc. Comput. Mach., vol. 11, pp. 283--295, 1964.
Reversible Logic Circuit Synthesis - Vivek Shende Aditya (2002) (Correct)
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E. Lawler, "An Approach to Multilevel Boolean Minimization," JACM, 11, July 1964, pp. 283-295.
Synthesis of Reversible Logic Circuits - Shende, Prasad, Markov, Hayes (2003) (Correct)
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E. Lawler, "An Approach to Multilevel Boolean Minimization," JACM, 11, `64, pp. 283-295.
Reversible Logic Circuit Synthesis - Shende, Prasad, Markov, Hayes (2002) (Correct)
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E. Lawler, "An Approach to Multilevel Boolean Minimization", J. of ACM, 11, No. 3, July 1964, pp. 283-295.
Absolute Bounds on Set Intersection and Union Sizes From.. - Rowe (1988) (3 citations) (Correct)
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E. L. Lawler, ""An approach to multilevel boolean minimization,"" Journal of the ACM, 11, 3,
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