B. K. Bray. Specialized Caches to Improve Data Access Performance. PhD thesis, Stanford University,May 1993. Home/Search Document Details and Download
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Understanding and Designing for Dependent Store/Load Pairs in.. - Bhargava (2000) (Correct)
....abilitytocombine several stores with contiguous addresses or the same address. Skadron and Clark discuss the issues and tradeo s involved in such a write bu er [53] Martonosi and Shaw did a study of the e ect of compilation techniques on the performance of a write bu er [35] Jouppi [29] and Bray [5] consider structures they call write caches with similar properties. The issues addressed in these papers and similar papers focus on 69 reducing the number of writes that are performed o chip and sometimes on chip. It is possible that mechanisms like the write bu er can be referred to as a ....
B. K. Bray. Specialized Caches to Improve Data Access Performance. PhD thesis, Stanford University,May 1993.
Design Issues and Tradeoffs for Write Buffers - Skadron (1997) (18 citations) (Correct)
....writes have priority at L2 Read bypassing, but underway writes are not preempted Table 2: Summary of the baseline write buffer model. Experiments focus on depth, retirement policy, and load hazard policy. it must evict one of its entries before writing that data to the next level. Bray and Flynn [3] also examine write caches. Goncalves and Appel [12] study the effects of cache write policy and write buffer configuration on their implementation of the ML language. They find performance of ML programs to be quite sensitive to these design choices. Mowry [20] briefly considers combining a write ....
B. K. Bray and M. J. Flynn. Specialized Caches to Improve Data Access Performance. PhD thesis, Stanford Computer Systems Laboratory, May 1993.
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