M. Pedram, "Logical-physical co-design for deep submicron circuits: challenges and solutions," in Proc. Asia and South Pacific Design Automation Conf., pp. 137--142, Feb. 1998.  Home/Search Document Details and Download
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Interconnect Performance Estimation Models for Synthesis and.. - Cong, Pan (1998) (1 citation) (Correct)
....buffer. The units are the same as in Table 3. We believe that these delay estimation models can be used in a wide spectrum of applications listed, but not limited, as follows: ffl Placement driven synthesis and mapping: One may keep a companion placement during synthesis and technology mapping [29, 30]. For every logic synthesis operation, the companion placement will be updated. Once the cell positions are known, one can use our delay estimation models to accurately predict interconnect performance and feed it into the synthesis engine. ffl RTL and physical level floorplan: During the sizing ....
M. Pedram, "Logical-physical co-design for deep submicron circuits: challenges and solutions," in Proc. Asia and South Pacific Design Automation Conf., pp. 137--142, Feb. 1998.
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