A. Chandrakasan, M. Potkonjak, J. Rabaey, R. Brodersen, "An Approach to Power Minimization Using Transformations", IEEE VLSI Signal Processing Workshop, 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....high power dissipation. The usual way of addressing I O pads performance and power dissipation is at the layout and circuit level [13] In this paper we consider I O power dissipation at a higher level of abstraction. The research on low power design has focused on the internal circuit [3] 4] [5], 6] 11] 18] despite the fact that the I O power dissipation is at least an important part if not the dominant factor in power dissipation [15] One reason is that the I O is considered somehow fixed or given . In high level synthesis the I O is likely to be a constraint on the design, ....

....between two consecutive time slots are clean . There are 64 transitions for a period of 16 time slots. This represents an average of 4 transitions per time slot, or 0.5 transitions per bus line per time slot. cause of increased power dissipation because they represent unnecessary transitions [3] [5]. This is why we consider a synchronous bus model in which the transitions between two consecutive time slots are clean (fig. 3) Latches are needed on the bus drivers side for such clean transitions. We ll consider the activity on a typical data bus to be characterized by a random uniformly ....

A. P. Chandrakasan, M. Potkonjak, J. Rabaey, R. W. Brodersen, "An Approach to Power Minimization Using Transformations", IEEE VLSI for Signal Processing Workshop, pp. , 1992, CA.

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A. Chandrakasan, M. Potkonjak, J. Rabaey, R. Brodersen, "An Approach to Power Minimization Using Transformations", IEEE VLSI Signal Processing Workshop, 1992.

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