J.Jain, A. Narayan, M. Fujita, and A. Sangiovanni-Vincentelli. Formal verification of combinational circuits. In VLSI Design Conf., pages 218--225, 1997.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....In fact, if equivalence checking can replace random simulation, such comparison will be more reliable. Because of the above reasons, equivalence checking becomes quite useful in hardware verification. Equivalence checking can be divided into two categories: combinational equivalence checking [6] and sequential equivalence checking [4] Combinational equivalence checking is based on Reduced Ordered Binary Decision Diagrams (ROBDDs) 2] which represents a circuit as a binary decision diagram. Bryant [2] proved that a circuit can be described as a reduced binary diagram which is a canonical ....

J. Jain, A. Narayan, M. Fujita, and A. Sangiovanni-Vincentelli, "Formal Verification of Combinational Circuits," VLSI Design, 1997.

....we believe that this is not a necessary consequence of using SAT methods vs. BDDs but rather a result of the specific SAT algorithms used and the way they have been applied in the overall methodology. This work is a preliminary attempt to validate this claim. A number of other approaches (see [4, 8] for a more detailed survey) addressing the CEC problem have appeared in the literature. However, they are omitted from the above survey since they are not directly relevant to the focus of this paper. 3 SAT Vs. BDDs in CEC denote the two combinational circuits being checked for equivalence. ....

J. Jain, A. Narayan, M. Fujita, and A. SangiovanniVincentelli. Formal verification of combinational circuits. In International Conference on VLSI Design, pages 218--225, January 1997.

....a small number of random inputs. Points in the circuits that behaved identically during simulation are considered to be possibly equivalent. Then, try to prove that the possibly equivalent points are indeed equivalent, using any equivalences we ve proven already to simplify the task. Jain et al. [16] survey a wide variety of these algorithms. Here, let s consider a simple example of how such an algorithm might work. Suppose we are comparing two large circuits. In the first step, we run, say, 64 random simulation vectors. Points in the two circuits that behaved identically for all 64 ....

J. Jain, A. Narayan, M. Fujita, andA. Sangiovanni-Vincentelli,"Formal Verification of Combinational Circuits," VLSI Design, 1997.

....and uninterpreted functions with equality (e.g. a = b implies f (a) f (b) regardless of what f is) This combination of theories was adequate for our purposes in most cases. 2. 5 Related Work We were inspired by the highly successful work on equivalence checking of combinational circuits (e.g. [7] is a recent survey) although at a technical level there are few similarities with our work. The key insights are that comparison of two very similar designs is an important practical problem and that conservatively exploiting that similarity greatly simplifies verification. The general software ....

Jawahar Jain, Amit Narayan, Masahiro Fujita, and Alberto Sangiovanni-Vincentelli. Formal verification of combinational circuits. In International Conference on VLSI Design, 1997.

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J.Jain, A. Narayan, M. Fujita, and A. Sangiovanni-Vincentelli. Formal verification of combinational circuits. In VLSI Design Conf., pages 218--225, 1997.

No context found.

J. Jain, A. Narayan, M. Fujita, and A. Sangiovanni-Vincentelli, "Formal Verification of Combinational Circuits," VLSI Design, 1997.

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