C. M. Woodside and R. G. Franks, "Alternative Software Architectures for Parallel Protocol Execution with Synchronous IPC," IEEE/ACM Transactions on Networking, vol. 1, Apr. 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....exhibit significantly different performance characteristics that are affected by the underlying operating system and hardware platform. For instance, on shared memory multi processor platforms, task based process architectures often result in high data movement and context switching overhead [5]. Likewise, in a messagepassing transputer multi processor environment, messagebased process architectures typically result in high levels of synchronization overhead [2] Existing research has generally selected a single type of process architecture (either task based or message based) and ....

....dynamism may enable message based process architectures to effectively use a larger number of PEs. 2.3 Related Work A number of studies have investigated the performance characteristics of task based process architectures developed to run on either message passing or shared memory platforms. [5] measures the impact of several implementations of the transport and session layers in the OSI reference model using an ADA like rendezvous style of Layer Parallelism in a nonuniform access shared memory environment. 9] measures the performance of a Functional Parallelism process architecture for ....

C. M. Woodside and R. G. Franks, "Alternative Software Architectures for Parallel Protocol Execution with Synchronous IPC," IEEE/ACM Transactions on Networking, vol. 1, Apr. 1993.

....is unable to provide the available throughput of a high speed network at transport level or application level due to a bottleneck in the protocol processing in higher layer protocols [Zitterbart 91] such as TCP or IP. For this reason many parallel processing approaches have been suggested [Woodside 91] While the static methods all introduce some kind of pipelining in the protocol stack which differ in the achievable granularity of parallel processing, the dynamic methods handle either incoming packets (packet parallelism [Goldberg 93] or whole connections (connection parallelism) For a ....

Woodside, C.M. and Franks, G. "Alternative Software Architectures for Parallel Protocol Execution with Synchronous IPC". IEEE/ACM Transactions on Networking, Vol. 1, No. 2, pp. 178--186, April 1993

....Computer Science University of Massachusetts Amherst, MA 01003 1 Introduction In this proposal, we explore scheduling issues in parallelized network protocol processing on shared memory multiprocessors. The use of parallelism in network processing has recently become an area of active research [6, 20, 31, 34, 39, 42, 49, 64, 65, 66, 80] and significant applied commercial interest [20, 31, 55, 64] The problem area is motivated in part by emerging high speed networks, such as ATM, capable of delivering gigabit range bandwidth to individual host endpoints. Emerging large scale server applications, such as digital information ....

....We begin with work which has explored functional and or pipelined parallelism. Many of these studies are primarily pencil and paper designs and provide little in the way of experimental results [7, 8, 29, 38, 41, 82] A few do describe actual implementation and present performance results [24, 39, 43, 42, 60, 80]. A theme that appears throughout is that the achievable speedup via functional and pipelined parallelism is generally limited by the uneven load balancing among functions and layers [24, 39, 43, 42, 82] Generally, the studies showing the greatest speedups have designed a new protocol with ....

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C. Murray Woodside and R. Greg Franks. Alternative software architectures for parallel protocol execution with synchronous IPC. IEEE/ACM Transactions on Networking, 1(2):178--186, April 1993.

....Multiprocessor front ends may be designed using specialpurpose or general purpose hardware. Special purpose designs facilitate efficient interaction with the host and the network interface unit [82, 83] while general purpose designs must explicitly coordinate accesses to these interfaces [14, 138, 182]. More processing power in the front end can improve the quality of service provided to the applications, by reducing queuing delays within the communication subsystem. Network interfaces for multicomputers: Network interface design for multicomputer environments presents unique opportunities and ....

.... general, communication subsystems employ one or more processes (or threads) to implement a protocol graph [76] Depending upon the allocation of work to these processes, communication subsystems can be classified into horizontal or vertical process architectures [152] In horizontal architectures [182], each process implements a specific layer of a protocol graph; at most two processes can be assigned to each layer, one each for transmission and reception. In vertical process architectures [14, 76, 83] on the other hand, processes are assigned to active entities such as connections or messages ....

C. M. Woodside and R. G. Franks, "Alternative software architectures for parallel protocol execution with synchronous IPC," IEEE/ACM Trans. Networking, vol. 1, no. 2, pp. 178--186, April 1993.

.... efficiency are discussed in [7] 8] 28] 10] and [32] Hardware implementations for high speed protocols have been proposed in [18] In the literature on optimised protocol implementation special attention has been paid to parallelising protocol implementations, so for example in [5] and [34]. However, the guidelines for parallelising proposed in these papers depend mainly on the intuition of the designer and thus its efficiency may be non optimal. Therefore, automated support when parallelising is desirable. 13] describes parallelising methods which have the per packet approach with ....

C. M. Woodside and R. G. Franks. Alternative software architectures for parallel protocol execution with synchronous IPC. IEEE/ACM Transactions On Networking, 1(2):178--186, April 1993.

.... architecture that increase an implementation s efficiency are discussed in [7] 8] 20] 9] and [23] Hardware implementations for high speed protocols have been proposed in [13] Special attention has been paid to the parallelization of protocol implementations, so for example in [5] and [24]. However, the parallelization proposed in these papers depends entirely on the intuition of the designer and thus its efficiency may be non optimal. Therefore automated support for the parallelization is desirable. An approach based on the scheduling of parallel tasks generated by an Estelle ....

C. M. Woodside and R. G. Franks. Alternative software architectures for parallel protocol execution with synchronous IPC. IEEE/ACM Transactions On Networking, 1(2):178--186, April 1993.

....such work provides only estimates of performance. Off host communications architectures have many similarities to parallel protocol implementations. To this end we wish to recognize the fine body of work on parallel implementations of network and transport protocols [6] 7] 16] 17] 20] 23] 25][49][50] 51] 52] This research is not surveyed here because it is largely concerned with issues intrinsic to parallel host computers rather than with the off host design issues presented in chapter two. 3.2. Chesson A pioneering effort in the development of off host protocol architectures was Greg ....

C. M. Woodside and R. G. Franks, "Alternative Software Architectures for Parallel Protocol Execution with Synchronous IPC," IEEE/ACM Transactions on Networking, Vol. 1, No. 2, April 1993, pp. 178-186.

.... increase an implementation s efficiency are discussed in [CJRS89] CT90] OP91] CWWS92] and [TW93] Hardware implementations for high speed protocols have been proposed in [KS89] Special attention has been paid to the parallelization of protocol implementations, so for example in [BZ92] and [WF93]. However, the parallelization proposed in these papers depends entirely on the intuition of the designer and thus its efficiency may be non optimal. Therefore automated support for the parallelization is desirable. An approach based on the scheduling of parallel tasks generated by an Estelle ....

C. M. Woodside and R. G. Franks. Alternative software architectures for parallel protocol execution with synchronous IPC. IEEE/ACM Transactions On Networking, 1(2):178--186, April 1993. A Formal Approach to Optimized Parallel Protocol Implementation 23

....entity (in these cases, the process) is much larger than the time required to entirely reload the referenced memory locations into the cache. In this paper, we explore the benefits of affinity scheduling of parallel networking, an area of research which has recently generated considerable interest [3, 4, 6, 12, 13, 15, 17, 18, 20, 23, 25, 26, 27, 35] and one for which affinity scheduling has not yet been examined. Intuitively, parallel networking is a potential candidate for the technique since packets can be individually scheduled and the time to process a packet is relatively short. However, several aspects of the application domain ....

C. Murray Woodside and R. Greg Franks. Alternative software architectures for parallel protocol execution with synchronous IPC. IEEE/ACM Transactions on Networking, 1(2):178--186, April 1993. (a) Impact of processor scheduling policy (b) Impact of thread pool and free-memory pool organization

.... VSTREAMS framework on multiprocessor versions of UNIX) fine grained task based parallelism results in prohibitively high levels of synchronization overhead [30] Likewise, asynchronous, rendezvous based task invocation semantics often result in high data movement and context switching overhead [31]. The remainder of this section summarizes the basic process architecture categories, classifies related work accordingly to these categories, and identifies several key factors that influence process architecture performance. ffl Task based Process Architectures: Task based process architectures ....

....strict adherence to the layer boundaries specified by conventional communication models (such as the ISO OSI reference model) complicates stage balancing. An empirical study of the performance characteristics of several software architectures for implementing Layer Parallelism is presented in [31]. Likewise, the XINU TCP IP implementation [32] uses a variant of this approach to simplify the design and implementation of its communication subsystem. ffl Functional Parallelism Functional Parallelism is a more fine grained task based process architecture that applies one or more processes ....

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C. M. Woodside and R. G. Franks, "Alternative Software Architectures for Parallel Protocol Execution with Synchronous IPC," IEEE/ACM Transactions on Networking, vol. 1, Apr. 1993.

.... PE active active active active active active active active active active active active active active MESSAGE MESSAGE PE PROCESSING PROCESSING ELEMENT ELEMENT PROTOCOL PROTOCOL TASK TASK Figure 1: Threading Architecture Components and Interrelationships caching properties of the OS and hardware [9]. In contrast, in a message passing multi processorenvironment, messagebased threading architectures exhibit high levels of synchronization overhead due to high latency access to global resources such as shared memory, synchronization objects, or connection context information [6] Prior work [1, ....

.... [9] In contrast, in a message passing multi processorenvironment, messagebased threading architectures exhibit high levels of synchronization overhead due to high latency access to global resources such as shared memory, synchronization objects, or connection context information [6] Prior work [1, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17] has generally selected a single task based or message based threading architecture and studied it in isolation. Moreover, earlier studies have been conducted on different OS and hardware platforms using different protocolstacks and implementation techniques. This diversity of threading ....

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C. M. Woodside and R. G. Franks, "Alternative Software Architectures for Parallel Protocol Execution with Synchronous IPC," IEEE/ACM Transactions on Networking, vol. 1, Apr. 1993.

....generated memory references are likely to be found in that processor s cache, thus avoiding accesses to the slower main memory and resulting in faster execution times. We study affinity based scheduling of parallel network protocol processing, which has recently become an area of active research [3, 8, 12, 14, 17, 20, 24, 34, 35, 36, 41] and significant applied commercial interest [8, 12, 29, 34] The use of parallelism in protocol processing is motivated by the development of high speed networks (such as ATM) capable of delivering gigabit range bandwidthto individualmachines. Emerging large scale server applications, such as ....

C. Murray Woodside and R. Greg Franks. Alternative software architectures for parallel protocol execution with synchronous IPC. IEEE/ACM Transactions on Networking, 1(2):178--186, April 1993.

....and of the parallel network interfaces cannot be exploited because of this I O bottleneck. Level Project Protocol Environment Stack [Ito93] OSI Layer 2 6 Multiprocessor Stack [Maly92] TCP IP Multiprocessor, Sparc10 Stack [R tsche93a] TCP IP, and ST II 2 Transputers plus VLSI (Analysis) Layer [Woodside93] OSI Transport and Session VME 68020 Multiprocessor Entity [Balraj92] Prompt Dedicated VLSI Entity [Blair93] OSI TP (95) Multi Transputer Entity [Braun92a] XTP, VMTP Multiple Transputer Entity [Chesson87] Schwaderer90] XTP Multiprocessor VLSI Entity [Diot91] TP4 Multiple Transputers VLSI ....

.... any Dedicated VLSI Operation [Sterbenz90] ALTP Dedicated VLSI Table 1: Main level of Parallelism exploited in various Projects 9 Project Stack Layer Entity Function Operation VLSI Protocol [Ito93] F CS OSI Layer 2 6 [Maly92] F TCP IP [R tsche93a] M M T CS,HP TCP IP, ST II (Analysis) Woodside93] T F OSI TP0 2 and Session [Balraj92] F M Yes Prompt [Blair93] T M OSI TP4 [Braun92a] M M XTP, VMTP [Chesson87] Schwaderer90] M M CS,HP B XTP [Chesson87] Schwaderer90] M M CS,HP B XTP [Diot91] M Yes TP4 [Jain90] F,T TP4 (Analysis) Kaiserswerth91] T,F M ISO 8802.2 2 [Kanakia88] VMTP ....

Woodside, C.M., Franks, R.G., "Alternative Software Architectures for Parallel Protcocol Execution with Synchronous IPC," IEEE/ACM Transactions on Networking, Vol.1, NO. 2, April 1993.

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C. M. WOODSIDE and R. G. FRANKS, "Alternative Software Architectures for Parallel Protocol Execution with Synchronous IPC," IEEE/ACM Transactions on Networking, 1 (April 1993).

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