Biesenack, J. "The Siemens High Level Synthesis System: CALLAS". Sixth International Workshop on High Level Synthesis (November 1992). Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Storage Optimization by Replacing Some Flip-Flops with Latches - Wu, Lin, al. (1996) (Correct)
....or the area of a circuit, a high level synthesizer can modify the behavior of any part of the circuit so long as the circuit s function matches what is specified in the behavioral description. However, because of their emphasis on the so called What You Synthesize is What You Simulate (WYSWYS [5][17] feature, contem porary HLS tools usually over synthesize by making sure that every node of the synthesized circuit exhibits identical timing behavior as that of the corresponding node in the behavioral specification. If we relax this WYSWYS restriction on the circuit interior, the ....
....will be able to save more chip area if some of the flip flops in a one phase clocked circuit can be replaced with latches. When a synchronous Mealy machine [9] is described in VHDL [2] the synchronization mechanism is usually expressed using a wait statement (e.g. wait until (clock= 1 ) 4][5]) Upon the execution of the wait statement, the machine must wait for the system clock to raise. In other words, each wait statement in the behavioral description leads to a state in the corresponding synchronous Mealy machine. For instance, in the 2 state machine synthesized from the behavioral ....
J. Biesenack, et al., "The Siemens High-Level Synthesis System CALLAS," IEEE Transactions on VLSI Systems, pp. 244-252, Sep. 1993.
Specification and Management of Timing Constraints in.. - Curatelli, Mangeruca, .. (1996) (Correct)
....semantics; all other statements that operate on variables can be executed at any time, given that the ordering imposed by the data dependencies is mantained. To ensure that the VHDL simulation timing semantics be satisfied also by the synthesized system, several approaches have been followed [1] [2] [10] 7] 15] 17] In particular, in [7] two methods are described for the synthesis of concurrent processes, which preserve a partial ordering relation of operations on signals and ports during synthesis. In the first method one is allowed to use freely signals and wait statements in the ....
J. Biesenack et al., "The Siemens High-Level Synthesis System CALLAS", IEEE Transactions on VLSI Systems, Vol. 1, No. 3, September 1993.
Recent Developments in High-Level Synthesis - Lin (1997) (15 citations) (Correct)
....such as Cathedral [55] Hyper [11] and Phideo [54] provide a design environment targeted towards the digital signal processing (DSP) applications with various levels of throughput requirements. In contrast to computational intensive DSP designs, many other HLS systems, such as HIS [7] Callas [53] and Olympus [62] have been targeted toward control dominated circuit designs. In addition, an HLS system Mimola Honeywell [101] has been targeted toward instruction set processor design. The System Architect s Workbench from CMU [89] has been used in designs for automotive applications [19] A ....
S. Ledeux et al., "The Siemens High Level Synthesis System CALLAS," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 1, No. 3, pp. 144-153, September 1993.
Synthesis of Systems Specified as Interacting VHDL Processes - Eles, Kuchinski, Peng (1995) (Correct)
....decisions. According to SynVHDL [7] and VSYNTH [11] for example, an architecture body may only contain a single process. Silicon 1076 [12] restricts the use of signal assignments to output ports and requires a design to contain only one process described at the architectural level. In CALLAS [13, 14, 15] the designer is required to use one explicit global clock signal. The entire behavior has to be described only in terms of variables, and the use of signals is practically limited to input and output ports. Papers dedicated specially to questions concerning the synthesis of signals, for example ....
J. Biesenack et. al., The Siemens High-Level Synthesis System CALLAS, IEEE Transactions on Very Large Scale Integration (VLSI), 1 (3) (1993) 244-253.
High Level Synthesis from Sim-nML Processor - Basu (1999) (Correct)
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Biesenack, J. "The Siemens High Level Synthesis System: CALLAS". Sixth International Workshop on High Level Synthesis (November 1992).
Dynamic Scan Testing: A New Paradigm - Part 3 - Gloster (1993) (Correct)
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J. Biesenack et. al. The Siemens High Level Synthesis System: CALLAS. In Sixth International Workshop on High Level Synthesis, November 1992.
Specification of Timing Constraints in VHDL for High-Level.. - Eles, al. (1994) (Correct)
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J. Biesenack, et. al., The Siemens High-Level Synthesis System CALLAS, IEEE Transactions on Very Large Scale Integration (VLSI), vol. 1, no. 3, September 1993, 233-243.
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