H. Kanakia and D. R. Cheriton: "The VMP Network Adapter Board (NAB): Highperformance network communication for multiprocessors", Proc. SIGCOMM '88, pp. 175-87, 1988 15  Home/Search   Document Not in Database   Summary   Related Articles   Check

....of these bottlenecks, and identified mechanisms that are at least partially effective in overcoming some of the handicaps. This is evidenced by the considerable litearature that has been published in recent years on network interface design, and on the structuring of protocols in operating systems [2,5,6,7,10,12,14,28,32,39,41]. We have attempted to integrate a number of these proven good mechanisms, along with some new ones of our own creation, in our attempt to build a state of the art high performance network interface. This document describes the design and implementation of this network interface chip (NIC) ....

....builds upon the success of these efforts by adopting a number of useful features and improving or improvising them for our target environment. 3.1. Related work in network interface design One of the earliest efforts in high speed network interface design was the network adapter board (NAB) [32], which was especially designed to support the VMTP transport protocol [4] As shown Figure 3.1: Network Adapter Board (NAB) Architecture Processor Host Interface Host Block Copier Memory Controller Checksum Logic Encryption Logic Network Link Host Bus 24 in Figure 3.1, the board ....

Kanakia, H., and Cheriton, D.R., "The VMP Network Adapter Board (NAB): High Performance Network Communication for Multiprocessors," Proc. ACM SIGCOMM 88, Aug. 1988.

....the performance of a given protocol [Cla89] These techniques depend on the environment more than on the protocol itself. The proposed solutions focused on the enhancement of the protocol implementation performance in a given software or a hardware environment: outboard protocol processors (e.g. [Kan88], Coo90] hardware protocol implementations (early work on XTP Protocol Engine [Che89] or parallel implementations of transport protocols [Bra92] Rut92] Lap92] Bjo93] A detailed survey of protocol implementation optimization techniques can be found in [Dab91] and [Fel93b] The ....

Hemant Kanakia, David R. Cheriton. "The VMP Network Adapter Board (NAB): High-Performance Network Communication for Multiprocessors", In Proceedings SIGCOMM '88, Stanford, CA, 1988, pp. 175-187.

....of indirection. However, this does not necessarily translate into longer execution time because of the execution communication overlap between the APs and the NP. Other systems have also used communication processors to improve network performance. The network adapter board of the VMP system [19] implements some link and network level protocols in the hardware. It is specifically designed for the VMTP protocol, and it provides a 4 PMMU 68851 Processor MC 68020 FPP 68881 4 MB Local Memory VMX Bus Interface VME Bus Interface Processor Card PMMU 68851 Processor MC 68020 FPP ....

H. Kanakia and D. R. Cheriton, "The VMP network adapter board (NAB): Highperformance network communications for multiprocessors," in Proceedings of the SIGCOMM Symposium, pp. 175--187. ACM, August 1988.

....load delay slots, and scoreboarding to minimize memory access delays; BibRef[39] describes an algorithm for checksumming with minimal loss of performance on architectures lacking carry bits. An alternate strategy is to implement the Internet checksum on the network adapter BibRef[4]BibRef[38]BibRef[57] but that requires extra adapter hardware or extra muscle from an onboard CPU. For example, DEC s FDDI adapter, which does not support onboard Internet checksum processing, is based on the relatively simple 16 bit MC68000 processor BibRef[55]BibRef[65] SGI s FDDI adapters, which do ....

H. Kanakia, D. R. Cheriton, "The VMP Network Adapter Board (NAB): HighPerformance Network Communication for Multiprocessors," Proceedings of the SIGCOMM `88 Symposium on Communications Architectures and Principles, pp. 175-187, 1988.

.... and the host processor [89, 164] Network adapters either facilitate flexibility in supporting different protocols through simple designs [46, 103, 120] or restrict flexibility, and hence improve performance, by supporting specific communication protocols and resource management strategies [37, 90]. In general, the overhead of host adapter interaction and unnecessary data movement across the system bus can limit the amount of useful concurrency between the software and hardware portions of the protocol stack, thus affecting communication subsystem performance. The design of high speed ....

....data copying or through shared memory. Not only does this permit special tuning of the functionality desired and significantly reduce the number of interrupts delivered to the host, it also permits exploitation of available concurrency through pipelining of the transmission and reception datapaths [90]. More importantly, it permits management of the communication subsystem by a separate executive designed for communication related operations, such as the x kernel [76] The VMP NAB [90] and Nectar CAB [120] are two examples of this functional partitioning. For example, the Nectar CAB [10, 120] ....

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H. Kanakia and D. R. Cheriton, "The VMP network adapter board (NAB): highperformance network communication for multiprocessors," Proc. of ACM SIGCOMM, pp. 175--187, August 1988.

....of operating systems such as UNIX, which are not well suited for asynchronous, interrupt driven network communication. For example, many operating system network to host interfaces generate interrupts for every transmitted and received packet, which increases the amount of CPU context switching [3, 4]. Moreover, despite increasing total MIPS, RISC CPUs often penalize interrupt driven network communication by exhibiting high context switching overhead. This overhead results from the cost of flushing pipelines, storing and retrieving register windows, and invalidating instruction data caches and ....

....the transport system. However, protocol and session architecture components may actually reside inside the OS kernel (BSD UNIX [8] and System V UNIX [7] in user space (Mach [20] and the Conduit [9] in either location (e.g. the x kernel [2] or in off board processors (Nectar [21] and VMP [4]) As shown by the shaded portions of Figure 2, this paper focuses on the protocol and kernel architectures. A thorough discussion of the application interface and session architecture levels is beyond the scope of this paper; they are included in Figure 2 for completeness and to provide a ....

H. Kanakia and D. R. Cheriton, "The VMP Network Adapter Board (NAB): High-Performance Network Communication for Multiprocessors," in SIGCOMM Symposium on Communications Architectures and Protocols, (Stanford, CA), pp. 175--187, ACM, Aug. 1988.

....that is not addressed the host. Similarly, a transport and network protocol processor can deliver to the host only those TSDUs which the host desires to receive, thus shielding it from an accidental or malicious barrage of TSDU arrivals. Such a feature has been referred to as a network firewall [27]. 1.4.2. Protocol Benefits A communications protocol can receive the following benefits when run on protocol processor hardware: Dedicated processing cycles. When run on the host, a communications protocol must contend with application processes for processor cycles, thereby losing potential ....

....no details of the command and status streams between the protocol processor and a user level application. 3.3. Kanakia and Cheriton Convinced that conventional transport protocols were too slow without hardware implementation, Kanakia and Cheriton designed the VMP 2 Network Adapter Board (NAB) [27]. The NAB is an off host protocol processor board designed to implement Cheriton s VMTP transport protocol [8] In their design, VMTP runs directly above the raw data link, i.e. the network layer of their protocol architecture is null. Like XTP, VMTP is a simplified, lightweight protocol, ....

[Article contains additional citation context not shown here]

H. Kanakia, D. R. Cheriton, "The VMP Network Adapter Board (NAB): High-Performance Network Communication for Multiprocessors," Proceedings of the SIGCOMM `88 Symposium on Communications Architectures and Protocols, August 1988, pp. 175-187.

....for parallel machine. Further more, ATM techonology, supporting finegrain multiplexing, provides a necessary condition of low latency communication in parallel and distributed computing [4] All of these has intensified the research toward designing high speed LAN based distributed systems [1][2] 3] An ATM based LAN provides better support for integrated services including data and real time multimedia applications. In the meanwhile, it also brings new challenges to LAN based distributed systems. We outline some of the new problems that need to be solved as follows. 1. The current ....

....In the meanwhile, it also brings new challenges to LAN based distributed systems. We outline some of the new problems that need to be solved as follows. 1. The current host to network interface imposes excessive overhead in the form of processor cycles, system bus capacity and host interrupts[1]. The memory system is accessed five times for each word of data sent and received [5] The host is interrupted by every received packet. With bursty traffic, the host merely has time to do any computation jobs while receiving packets. 2. With traditional synchronous send receive model, the sender ....

Kanakia,H. and Cheriton,D.R. "The VMP Network Adapter Board (NAB) High Performance Network Communication for Multiprocessors, " Proc. of the SIGCOMM `88

.... While less frequent polling improves throughput and host performance, it has some potentially negative consequences for latency; for example a 60 Hertz timer would give a worst case latency of over 16.7 milliseconds before data reached a process, far slower than desired for many LAN applications [Kanakia 88] This is easily observable on our systems using ping and changing the clocked interrupt rate on the system being pinged. Our system goal was high throughput, and other considerations (e.g. the distance to MIT) were expected to dominate round trip times. As we will see when analyzing TCP IP ....

Hemant Kanakia and David R. Cheriton, "The VMP Network Adapter Board (NAB): High Performance Network Communication for Multiprocessors," in Proceedings, ACM SIGCOMM '88 (August 16-19 1988), pp. 175-187.

....high performance host interfaces. One major difference between these implementations is the number of protocol processing functions which the host interface performs. One important focus has been interfaces which accelerate transport protocol processing [23] For example, Kanakia and Cheriton s [16] VMP Network Adapter Board serves as a hardware implementation of Cheriton s Versatile Message Transaction Protocol (VMTP) Abu Amara, et al. 1] can target any set of protocol layers (to the degree that they can be precisely specified) with their PSi silicon compiler approach. With this method, ....

H. Kanakia and D. Cheriton, "The VMP Network Adapter Board (NAB): High Performance Network Communication for Multiprocessors," in Proceedings, SIGMETRICS '88 (1988).

....such as UNIX, consequently the availability of new hardware technologies has not been exploited to the fullest. This has made existing operating systems become a bottleneck in end systems. Well known overheads include data copying, network protocol processing, context switches, and interrupts [13] [19] 16] Several techniques have been proposed and implemented to avoid these overheads [7] 6] 10] 18] In this work, we minimized data copying by using a UNIX kernel which supports single copy TCP IP, a modified version of TCP IP. Throughout this paper, we refer to two copy TCP IP as ....

H. Kanakia and D. Cheriton. "The VMP Network Adapter Board (NAB): HighPerformance Network Communications for Multiprocessors," in Proc. ACM SIGCOMM 1988, Symposium on Communication Architectures and Protocols, pp. 175-187.

....of address recognition in bridges. However, there are a number of other applications in computer networks where caching can help avoid searching through a number of entries. For example, datalink adapters can use caching to search through the list of multicast addresses. The network adapter board [11] uses caching to help decode the received frame header. Routers and gateways can cache forwarding databases. Also, name servers and their clients can use caching to improve the efficiency of name lookup. Although, the conclusions of our reference trace are not applicable to these other ....

H. Kanakia and D. R. Cheriton, "The VMP Network Adapter Board (NAB): High-Performance Network Communication for Multiprocessors," Proc. SIGCOMM'88, Stanford, CA, August 1988, pp. 175-197.

.... less frequent polling improves throughput and host performance, it has some potentially negative consequences for latency; for example a 60 Hertz timer would give a worst case latency of over 16.7 milliseconds before data reached an application, far slower than desired for many LAN applications [Kanakia 88] This is easily observable on our systems using ping and changing the clocked interrupt rate on the system being pinged. When we designed our system, the focus was throughput, and other considerations (e.g. the distance to MIT) were expected to dominate round trip times. As we will see when ....

Hemant Kanakia and David R. Cheriton, "The VMP Network Adapter Board (NAB): High Performance Network Communication for Multiprocessors," in Proceedings, ACM SIGCOMM '88 (August 16-19 1988), pp. 175-187.

.... increased by 2 or 3 orders of magnitude (from 1 MIP up to 100 MIPS) 3] 2) existing transport systems are written largely in software, 3) network host interfaces typically generate interrupts for every transmitted and received packet, leading to increased CPU context process switching overhead [3, 9], and (4) despite increasing total MIPS, RISC architectures often penalize interrupt driven network communication by exhibiting high context process switching overhead. This overhead results from the cost of flushing instruction and data caches and pipelines, as well as from storing and retrieving ....

....faster hardware for CPUs, busses, network controllers, and memory hierarchies. 2. Implement selected functions (e.g. checksum calculations, message buffering, and demultiplexing) in special purpose hardware. 3. Migrate some or all of the protocol processing activities to off board processors [9, 20, 32] to reduce CPU interrupts and operating system context process switching on the host computer. 4. Implement existing protocols more efficiently by (1) shortening the instruction paths executed for each packet and (2) improving the implementation of standard transport system support services such ....

H. Kanakia and D. R. Cheriton, "The VMP Network Adapter Board (NAB): High-Performance Network Communication for Multiprocessors," in Proceedings of the Symposium on Communications Architectures and Protocols (SIGCOMM), (Stanford, CA), pp. 175--187, ACM, Aug. 1988.

....It is also exacerbated by the widespread use of operating systems that are not wellsuited to asynchronous, interrupt driven network communication. For example, many network adapters generate interrupts for every transmitted and received packet, which increases the number of CPU context switches [3, 4]. Despite increasing total MIPS, RISC based computer architectures exhibiting high context switching overhead that penalizes interrupt driven network communication. This overhead results from the cost of flushing pipelines, invalidating CPU instruction data caches and virtual memory ....

....the nucleus of the transport system. However, protocol and session architecture components may reside within an OS kernel (BSD UNIX [8] and System V UNIX [7] in user space (Mach [22] and the Conduit [9] in either location (the x kernel [2] or in off board processors (Nectar [23] and VMP [4]) the execution of instructions within an address space. This address space may be shared with other processes. Other terms (such as threads [24] are often used to denote the same basic concept. Our use of the term process is consistent with the definition adopted in [25] A process ....

H. Kanakia and D. R. Cheriton, "The VMP Network Adapter Board (NAB): High-Performance Network Communication for Multiprocessors," in Proceedings of the SIGCOMM Symposium on Communications Architectures and Protocols, (Stanford, CA), pp. 175--187, ACM, Aug. 1988.

....we are to be able to meet the demands imposed by our choice of target applications. 3 Related Work Several research groups have attempted to design and implement high speed host network interfaces over the past few years [10] One of the earliest efforts include the network adaptor board (NAB) [11], which was especially designed to support the VMTP transport protocol [5] Important aspects of this interface include clever partitioning of protocol processing between the host CPU and a general purpose onboard microprocessor, and the use of a VRAM to allow concurrent protocol processing and ....

Kanakia, Hemant; and Cheriton, David R.; "The VMP Network Adapter Board (NAB): High Performance Network Communication for Multiprocessors", Proc. ACM SIGCOMM `88, Vol. 18 No. 4, 1988, pp. 175-187.

....R. Cox, Jr. jrc cs.wustl.edu The APIC Approach to High Performance Network Interface Design Page 1 1 Introduction Network interface design and the structuring of protocol implementations in operating systems are two areas of research that have received considerable attention in recent years [1,3,4,5,7,8,9,22,23,28,30]. The sudden interest in these subjects can be attributed to the observed gross disparity between the raw bandwidth available from emerging gigabit networks, and the maximum effective throughput that can be delivered to end applications. The bottlenecks in end systems that give rise to this ....

Kanakia, H., and Cheriton, D.R., "The VMP Network Adapter Board (NAB): High Performance Network Communication for Multiprocessors," Proc. ACM SIGCOMM 88, Aug. 1988.

....if we are to be able to meet the demands imposed by our choice of target applications. 3 Related Work Several research groups have attempted to design and implement high speed host network interfaces over the past few years [2] One of the earliest efforts include the network adaptor board (NAB) [16], which was especially designed to support the VMTP transport protocol [6] Important aspects of this interface include clever partitioning of protocol processing between the host CPU and a general purpose on board microprocessor, and the use of a VRAM to allow concurrent protocol processing and ....

Kanakia, Hemant; and Cheriton, David R.; "The VMP Network Adapter Board (NAB): High Performance Network Communication for Multiprocessors", Proc. ACM SIGCOMM `88, Vol. 18 No. 4, 1988, pp. 175-187.

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H. Kanakia and D. R. Cheriton: "The VMP Network Adapter Board (NAB): Highperformance network communication for multiprocessors", Proc. SIGCOMM '88, pp. 175-87, 1988 15

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H. Kanakia, D. Chefiron, The VMP Network Adapter Board NAB: High-Performance Network Communication for Multiprocessors, Proceedings of 1988.

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Cheriton, D.R. and Kanakia, H., "The VMP Network Adapter Board (NAB): HighPerformance Network Communication for Multiprocessors", ACM SIGCOMM '88, Stanford, California, August 1988, pp. 175-187.

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H. Kanakia and D. Cheriton, "The VMP Network Adapter Board (NAB): High Performance Network Communication for Multiprocessors," Proceedings of the Symposium on Communications Architectures and Protocols, ACM SIGCOMM 1988, ACM Computer Communication Review, vol. 18, no. 4 (August 1988).

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Kanakia, H., Cheriton, D. "The VMP Network Adapter Board (NAB): High Performance Network Communication for Multiprocessors", Proceedings of SIGCOMM-88, pp. 175187, August 1988. ATOMIC: A Low-Cost, Very-High-Speed LAN 22 of 22

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H. Kanakia and D.R. Cheriton. "The VMP Network Adapter Board (NAB): High-performance Network Communication for Multiprocessors." In Proceedings of the ACM SIGCOMM '88 Symposium on Communication Architectures and Protocols. 1988.

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Hemant Kanakia and David R. Cheriton, "The VMP Network Adapter Board (NAB): High-Performance Network Communication for Multiprocessors," ACM SIGCOMM '88 Symposium, Stanford, CA, Aug. 16-19, 1988, pp. 175187.

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