Heddes, M., "A Model and Implementation Strategies for Fine--Grain Parallelism in Protocol Processing," PhD. Thesis Univ. of Eindhoven,  Home/Search   Document Not in Database   Summary   Related Articles

....cannot be performed efficiently by a general purpose microprocessor. A significant improvement can be obtained when 4. Another challenge is to design novel hardware architectures for protocol processing. This is not the topic of the present paper, more details can be found in for example [Heddes93] 5 these functions are performed by dedicated hardware or VLSI. Fine grain parallelism is obtained by splitting the protocol implementation into a large number of concurrently operating processes. Implementing each process on a conventional microprocessor may have two disadvantages. First, ....

.... TCP IP 4 Transputers with shared memory Entity [Steenkiste92] TCP IP 2 processors VLSI Entity [Ulrich90] TP4 Transputer with shared memory Function [Braun92b] PATROCLOS (Transputer) Function [Koufopavlou92] TCP VLSI (Analysis) Function [Zitterbart91] TP4 Multiple Transputers Operation [Heddes93] any Dedicated VLSI (Analysis) Operation [Krishnakumar92] LAPD Dedicated VLSI Operation [Sidenius90] any Dedicated VLSI Operation [Sterbenz90] ALTP Dedicated VLSI Table 1: Main level of Parallelism exploited in various Projects 9 Project Stack Layer Entity Function Operation VLSI Protocol ....

[Article contains additional citation context not shown here]

Heddes, M., "A Model and Implementation Strategies for Fine--Grain Parallelism in Protocol Processing," PhD. Thesis Univ. of Eindhoven,

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC