D.M. Miller, "Multiple-valued logic design tools," Proc. International Symposium on Multiple Valued Logic, pp.2--11, May 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....done frequently for minimization of the node count. Often most of the runtime is spent on variable re ordering. An optimization method that performs dynamic re ordering and has been applied to this problem successfully is sifting. It has originally been presented for BDDs [14] and Miller showed in [12] that it is also feasible for MDDs. By sifting, significant size reductions can be achieved, but on the other hand, the algorithm is rather time consuming. Methods to speed up sifting have been proposed one example is relaxed lower bound sifting for MDDs [10] Since there is a trade off ....

....variable orderings for DDs is computationally hard [2] and therefore in general heuristics have to be used to reduce MDD sizes. Dynamic re ordering (by sifting) is the state of the art technique for variable ordering optimization. It has originally been presented for BDDs [14] and Miller showed in [12] that it is also feasible for MDDs. MDD sifting is realized by group sifting of BDD variables in the approach presented in our paper. Therefore, sifting is introduced for BDDs first followed by a description of how the method can be adapted in order to sift multi valued variables that are realized ....

D. Miller. Multiple-valued logic design tools. In Int'l Symp. on Multi-Valued Logic, pages 2--11, 1993.

.... this paper, we consider representations of two valued logic functions using quasi reduced multi valued decision diagrams with # bits (QRMDD(#)s) As for methods to represent logic functions by decision diagrams (DDs) binary decision diagrams (BDDs) 1, 7] and multi valued decision diagrams (MDDs) [3, 10, 12, 14] are known. Especially, MDDs require fewer nodes than corresponding BDDs. Also, the number of memory accesses required in MDDs is smaller than corresponding BDDs [12] In this paper, we show relations among the amount of memory to represent QRMDD(#) the number of memory accesses, and values of ....

D. M Miller, "Multiple-valued logic design tools," Proc. of International Symposium on Multiple Valued Logic, pp. 2-- 11, May 1993.

....the calculation of the worst case number of nodes, the first of which is Ross et al. 8] In the second, Heap [6] presented a correction to the results in [8] Independently, Sasao [9] derived a similar expression. The last paper is an example of the growing number of papers on MDDs, e.g. Miller [7]. Within binary, we know of only one other paper devoted to the average number of nodes in a class of switching functions. Butler and Sasao [3] consider a special class of threshold functions called Fibonacci functions. An interesting and important question is whether the typical BDD of a ....

D.M. Miller, "Multiple-Valued Logic Design Tools," Proc. 23rd Int'l Symp. Multiple-Valued Logic, pp. 2-11, May 1993.

....the data structure. Many problems in practice require the transformation of symbolic variables to a binary encoding for getting accessible with OBDDs or POBDDs. Extending the OBDD data structure from the binary domain to a nite domain results in so called Multi valued Decision Diagrams (MDDs) [5] and a binary encoding of symbolic variables is not necessary anymore. The already introduced POBDDs can now be extended towards Mod p Decision Diagrams (Mod p DDs) i.e. MDDs with additional operator nodes representing an integer addition modulo p, p 1 prime. Such decision diagrams have a ....

D. M. Miller, Multiple-valued logic design tools, Proc. 23rd Int. Symp. on MVL (1993), 2-11.

....discrete functions. Among them, graph based representations such as BDDs (binary decision diagrams) are extensivelyusedinlogicsynthesis, test, and verification [4] Multiple valued decision diagrams (MDDs) are multiple valued extensions of BDDs, and have been used to design logic networks [14, 8, 5, 9, 10]. Recently, McGeer et al. developed a logic simulator based on MDDs [12] They showed that the MDD based simulator is orders of magnitude faster than a conventional one. Their method is summarized as follows: 1. Represent a given logic function by a BDD. 2. Group k variables into a single 2 k ....

D. M. Miller, "Multiple-valued logic design tools," Proc. of International Symposium on Multiple ValuedLogic, May 1993, pp. 2-11.

....presented the concept of AND TDDs and SOP TDDs, and analyzed their complexities. Later his group successfully minimized FPRM, a class of ANDEXOR two level logic expressions, with more than 90 input variables by using EXOR TDDs [60] Heap Rogers Mercer [15] used EXOR TDD to simplify ESOPs. Miller [34] implemented an MDD reduction algorithm, where he considered unary cycling operations to simplify MDDs [35] McGeer McMillan Saldanha SangiovanniVincentelli Scaglia [31] used MDD in cycle based logic simulation. They grouped k binary input variables to form a single 2 k valued variable. By ....

D. M. Miller, "Multiple-valued logic design tools," Proc. of International Symposium on Multiple Valued Logic, May 1993, pp. 2-11. 9

.... circuits, such as random simulation or symbolic simulation, can be directly applied to verification of multiple valued logic case [4] 5] Similarly, verification procedures employing Reduced Ordered Binary Decision Diagrams (ROBDDs) 6] can adapted to Multiple valued Decision Diagrams (MDD) [7] as shown in [8] However, the MDD verification methods representing functions as single, monolithic graph might be infeasible for large functions. We believe that deterministic methods of verification will not be practical for the multiple valued logic domain due to the increasing complexity of ....

D. M. Miller, Multiple-valued logic design tools, Proc. 23rd Int. Symp. on Multiple-Valued Logic (1993), 2-11.

....and Calculus of Rough Partitions in the past. II. Representation of Incompletely Specified Multi Valued Functions Two essentially different representation methods for MV functions are used in programs: Multiple Valued Cube Calculus (MVCC) 23] and Multiple Valued Decision Diagrams (MVDD) [14, 5]. These methods have also been extended to incompletely specified functions. Here we will focus on the area that has not been researched until recently: very weakly specified functions, specified by very many variables but with relatively small percentage of care minterms, i.e. input combinations ....

D.M. Miller, "Multiple-valued logic design tools," in Proc. ISMVL, pp. 2-11, 1993.

....For the case of Boolean functions, Reduced Ordered Binary Decision Diagrams (ROBDDs) 1] have proved to be well quali ed for this purpose. ROBDDs can be extended to discrete case in di erent ways, depending on the decomposition applied to the function in the nodes of the diagram. For example, [2] presented a generalization of ROBDDs to Multiple Valued Decision Diagrams (MDDs) representing multiple valued functions of type M n M , over a nite set of totally ordered values M = f0; 1; m 1g. The conventional ITE algorithm is extended for this purpose to the CASE algorithm, ....

....several di erent signatures per node with di erent random assignment from GF (p k ) 7 4 Operations on Mod p DDs In this section we describe operations involved in reduction and synthesis of Mod p DDs. 4. 1 Reduction rules for Mod p DDs Mod p DDs can be reduced in the same manner as MDDs [2], 13] In a Mod p DD, a branching node is redundant if all p of its out coming edges point to the same node. Then, the node can be replaced by reconnecting all its incoming edges to its child. This reduction rule is called simple reduction or deletion rule. Identi cation of isomorphic subgraphs ....

D. M. Miller, Multiple-valued logic design tools, Proc. 23rd International Symp. on MVL (1993), 2-11.

....For the case of Boolean functions, Reduced Ordered Binary Decision Diagrams (ROBDDs) 4] have proved to be well quali ed for this purpose. ROBDDs can be extended to discrete case in di erent ways, depending on the decomposition applied to the function in the nodes of the diagram. For example, [5] presented a generalization of ROBDDs into Multiple Valued Decision Diagrams (MDDs) representing multiple valued functions, M n M , over a nite set of totally ordered values M = f0; 1; m 1g. For this purpose the conventional ITE algorithm [6] is extended into the CASE algorithm, ....

....therefore it can be reduced by enlarging the size of the eld. It can also be reduced by using several di erent signatures per node with di erent random assignment from GF (p k ) 4 Operations on Mod p DDs 4. 1 Reduction rules for Mod p DDs Mod p DDs can be reduced in the same manner as MDDs [5], 17] In a Mod p DD, a branching node is redundant if all p of its out going edges point to the same node. Then, the node can be replaced by reconnecting all its incoming edges to its child (simple reduction or deletion rule) Identi cation of isomorphic subgraphs forms the second reduction rule ....

D. M. Miller, Multiple-valued logic design tools, Proc. 23rd Int. Symp. on MVL (1993), 2-11.

....For the case of Boolean functions, Reduced Ordered Binary Decision Diagrams (ROBDDs) 1] have proved to be well qualified for this purpose. ROBDDs can be extended to discrete case in different ways, depending on the decomposition applied to the function in the nodes of the diagram. For example, [2] presented a generalization of ROBDDs into MultipleValued Decision Diagrams (MDDs) representing multiplevalued functions M n M , over a finite set of totally ordered values M = f0; 1; m 1g. The conventional ITE algorithm is extended for this purpose into the CASEalgorithm, utilizing ....

....several different signatures per node with different random assignment from GF (p k ) 4 Operations on Mod p DDs In this section we describe operations involved in reduction and synthesis of Mod p DDs. 4. 1 Reduction rules for Mod p DDs Mod p DDs can be reduced in the same manner as MDDs [2], 13] In a Mod p DD, a branching node is redundant if all p of its out coming edges point to the same node. Then, the node can be replaced by reconnecting all its incoming edges to its child (simple reduction or deletion rule) Identification of isomorphic subgraphs forms the second reduction ....

D. M. Miller, Multiple-valued logic design tools, Proc. 23rd Int. Symp. on MVL (1993), 2-11.

.... circuits, such as random simulation or symbolic simulation, can be directly applied to veri cation of multiplevalued logic case [4] 5] Similarly, veri cation procedures employing Reduced Ordered Binary Decision Diagrams (ROBDDs) 6] can adapted to Multiple valued Decision Diagrams (MDD) 1 [7]. However, the MDD veri cation methods representing functions as single, monolithic graph might be infeasible for large functions. We believe that deterministic methods of veri cation will not be practical for the multiple valued logic domain due to the increasing complexity of the problem. In ....

D. M. Miller, Multiple-valued logic design tools, Proc. 23rd Int. Symp. on Multiple-Valued Logic (1993), 2-11.

....can be used to guide the choice of polarity and also to investigate which search techniques are applicable to this problem. Further work on the efficiency of computing the expressions might also incorporate representation of multiplevalued functions by Multiple Valued Decision Diagrams (MDD) [19], and performing the basic operations of the algorithm directly on graphs. Since there is no direct correspondence between the size of the cover for the function and the size of the MDD that represents it, very large cube covers can be captured and efficiently manipulated using this ....

D. M. Miller, Multiple-valued logic design tools, Proc. 22rd International Symp. on MVL (1993), 2-11.

.... all the circuits can be directly realized using the primitives proposed, we also aim at transform based design methods that are emerging in the modern logic synthesis [116] One such application is the synthesis using FPGAs [12] in conjunction with the recently introduced MVL FPGA architectures [78], 130] 21 Chapter 3 Current mode Galois Field Circuits This chapter presents an application of MVL current mode CMOS technology in the realization of Galois field operations. The Galois field multiplier and adder are elaborated in detail, while the circuits that perform the other operations ....

Miller, D. M., Multiple-Valued Logic Design Tools, Proceedings of the 23rd ISMVL, pp. 2-11, May 1993.

....cases occur (see Figure 1) 3 . In [27] it was shown that it is even possible to perform LEs as local operations when using DDs with CEs. LE for FDDs, OKFDDs, ZBDDs and MTBDDs works likewise. For MDDs the exchange of neighbouring variables is applied by a rearrangement of multiple grand sons [22, 14]. 3 Reordering Based Synthesis Approach The basic idea of MORE (based on existential quantification and restricted to the OR operation only) and an extension to RBS was first introduced for BDDs in [19, 20] Here we propose a general approach of Reordering Based Synthesis for DD types mentioned ....

....Further studies are needed to see whether the concept can also be applied to these more general data structures. MDD [30] The RBS principle can also be applied in the case of several outgoing edges per node. This is due to the fact that also for MDDs dynamic reordering methods can be applied [22, 14]. But it has to be considered that for each exchange at most k Delta (k Gamma 1) pointers must be redirected. In addition (since the Operator Variables might have less than k outgoing nodes) the implementation has to deal with different node sizes. This problem is similar to dealing with ....

D.M. Miller. Multiple-valued logic design tools. In Int'l Symp. on multi-valued Logic, pages 2--11, 1993.

....package. 1. Introduction Reduced ordered binary decision diagrams (BDD) have been widely studied since their introduction by Bryant [2] in 1986. A good review can be found in [3] and the other articles included in that special issue. The extension to multiple valued logic has been considered [7,8,9,15]. In the MVL case, a function is represented by a directed acyclic graph called a multiple valued decision diagram (MDD) MDDs are ordered and reduced in a fashion analogous to the binary case and the resulting representation is termed a reduced ordered MDD. Since all diagrams considered in this ....

Miller, D.M., "Multiple-valued logic design tools," (Invited Address) Proc. 23rd Int. Symp. on MultipleValued Logic, pp. 2-11, May 1993.

....We need to incorporate a more sophisticated cost measure, reflecting the specific of the target architecture. Further work on the efficiency of the algorithm might also incorporate representation of multiple valued input binary valued output functions by Multiple Valued Decision Diagrams (MDD) [21], and performing the basic operation of the algorithm directly on graphs. Since there is no direct correspondence between the size of the cover for the function and the size of the MDD that represents it, very large cube covers can be captured and efficiently manipulated using this ....

D. M. Miller, "Multiple-valued logic design tools", Proc. 23rd Int. Symp. MultipleValued Logic, May 1993, pp. 2-11.

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D.M. Miller, "Multiple-valued logic design tools," Proc. International Symposium on Multiple Valued Logic, pp.2--11, May 1993.

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D. M Miller, "Multiple-valued logic design tools," Proc. of International Symposium on Multiple Valued Logic, pp. 2--11, May 1993.

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D. M. Miller,"Multiple-valued logic design tools", ISMVL-93, May 1993, pp. 2-11.

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D. M Miller, "Multiple-valued logic design tools," Proc. International Symposium on Multiple Valued Logic, pp.2--11, May 1993.

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D. M Miller, "Multiple-valued logic design tools," Proc. of International Symposium on Multiple Valued Logic, pp. 2--11, May 1993.

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D. M Miller, "Multiple-valued logic design tools," Proc. of International Symposium on Multiple Valued Logic, pp. 2--11, May 1993.

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