Balraj, T.; Yemini, Y.; Putting the Transport Layer on VLSI - the PROMPT Protocol Chip; in: Pehrson, B.; Gunningberg, P.; Pink, S. (eds.): Protocols for High-Speed Networks, III, 1992, North-Holland, pp. 19-34  Home/Search   Document Not in Database   Summary   Related Articles   Check

....the approaches deal with efficient implementations of standard protocols such as OSI TP4 or TCP. Others developed protocols especially suited for advanced implementation environments. The use of dedicated VLSI components is mostly limited to very simple communication protocols, only (e.g. 5] [6]) In this paper, we present a VLSI architecture that is especially targeted towards more complex protocols. Connection oriented protocols with advanced protocol mechanisms can be implemented on this architecture. Specific support for processing intensive functions is provided. For example, ....

....appropriate interface (e.g. DMA interface) for data transfer between host memory and send receive RAM. To avoid buffering of data within the send receive memory, the user data may also be copied directly from the network component into the workstation memory. The basic architecture is similar to [6]. The CPs are responsible for implementing the transport protocol of the communication subsystem. As long as enough free processing power of the CPs is available, a connection can be mapped onto a CP. However, parallelism in protocol implementation is not the major issue addressed in this paper. ....

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Balraj, T.; Yemini, Y.; Putting the Transport Layer on VLSI - the PROMPT Protocol Chip; in: Pehrson, B.; Gunningberg, P.; Pink, S. (eds.): Protocols for High-Speed Networks, III, 1992, North-Holland, pp. 19-34

....Some of the approaches deal with efficient implementations of standard protocols such as OSI TP4 or TCP. Others developed protocols especially suited for advanced implementation environments. The use of dedicated VLSI components is mostly limited to very simple communication protocols (e.g. 7] [8]) Another issue in the evolution is the increasing importance of group communication scenarios. Upcoming applications, for example in the areas of computersupported co operative work (CSCW) distributed systems, and virtual shared memory systems require point to multipoint (Multicast, 1:N) as ....

Balraj, T.; Yemini, Y.; Putting the Transport Layer on VLSI - the PROMPT Protocol Chip; in: Pehrson, B.; Gunningberg, P.; Pink, S. (eds.): Protocols for High-Speed Networks, III, 1992, North-Holland, pp. 19-34

.... found in [1] Some of the approaches deal with efficient implementations of standard protocols, such as OSI TP4 or TCP (e.g. 2] 3] Others developed protocols specially suited for parallel implementations, such as XTP [4] TP [5] MSP [6] 7] AXON [8] or PATROCLOS [9] Moreover, 10] and [11] specifically deal with the VLSI implementation of simple protocols. The parallel VLSI architecture presented in this paper is especially targeted towards more complex communication protocols, such as connection oriented protocols. Moreover, the architecture is highly independent of the specific ....

....data copies during protocol processing. Operations on the memory, such as segmentation reassembly and allocation deallocation, are completely handled by the EMMUs. Applications may read and write data via DMA. A key feature of the architecture is the replication of identical CPs similar to [11] for different connections. They include registers, arithmetic logical units (ALUs) timers, and other components required in a protocol implementation. The main purpose of the remaining components (management, A MUX, N MUX, N DMX) is the distribution and collection of relevant data. Received data ....

Balraj, T.; Yemini, Y.; Putting the Transport Layer on VLSI - the PROMPT Protocol Chip; in: Pehrson, B.; Gunningberg, P.; Pink, S. (eds.): Protocols for High-Speed Networks, III, 1992, North-Holland, pp. 19-34

....this I O bottleneck. Level Project Protocol Environment Stack [Ito93] OSI Layer 2 6 Multiprocessor Stack [Maly92] TCP IP Multiprocessor, Sparc10 Stack [R tsche93a] TCP IP, and ST II 2 Transputers plus VLSI (Analysis) Layer [Woodside93] OSI Transport and Session VME 68020 Multiprocessor Entity [Balraj92] Prompt Dedicated VLSI Entity [Blair93] OSI TP (95) Multi Transputer Entity [Braun92a] XTP, VMTP Multiple Transputer Entity [Chesson87] Schwaderer90] XTP Multiprocessor VLSI Entity [Diot91] TP4 Multiple Transputers VLSI Entity [Jain90] TP4 Analysis Entity [Kaiserswerth91] ISO 8802.2 2 ....

.... ALTP Dedicated VLSI Table 1: Main level of Parallelism exploited in various Projects 9 Project Stack Layer Entity Function Operation VLSI Protocol [Ito93] F CS OSI Layer 2 6 [Maly92] F TCP IP [R tsche93a] M M T CS,HP TCP IP, ST II (Analysis) Woodside93] T F OSI TP0 2 and Session [Balraj92] F M Yes Prompt [Blair93] T M OSI TP4 [Braun92a] M M XTP, VMTP [Chesson87] Schwaderer90] M M CS,HP B XTP [Chesson87] Schwaderer90] M M CS,HP B XTP [Diot91] M Yes TP4 [Jain90] F,T TP4 (Analysis) Kaiserswerth91] T,F M ISO 8802.2 2 [Kanakia88] VMTP [Laouar92] T M ISO 8802.2 2 [La Porta92] ....

Balraj, T., Yemini, Y.,"Putting the Transport Layer on VLSI -- the PROMPT protocol chip," 3rd. Int IFIP WG.6.1 Workshop on Protocols for High--Speed Networks, Stockholm May 1992.

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