E. M. McCreight. The Dragon Computer System, an Early Overview. In NATO Advanced Study Institute on Microarchitecture of VLSI Computers, July 1984.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....In these networks contention for links and buffers is captured at the source and destination of messages. All our architectural parameters are compatible with those of scalable multiprocessors such as DASH. In order to keep caches coherent we used write invalidate (WI) 7] and writeupdate (WU) [12] protocols. In the WI protocol, whenever a processor writes a data item, copies of the cache block containing the item in other processors caches are invalidated. If one of the invalidated processors later requires the same item, it will have to fetch it from the writer s cache. Our WI protocol ....

E. M. McCreight. The Dragon Computer System, an Early Overview. In NATO Advanced Study Institute on Microarchitecture of VLSI Computers, July 1984.

....leftmost goal or branch to execute cuts or side effects. The sharing of writable data structures introduces the problem of coherence between the processors caches. Most parallel machines have used a write invalidate (WI) protocol [5] in order to keep caches coherent. Write update (WU) protocols [8] are the main alternative to invalidatebased protocols. WI protocols have been more popular than WU protocols because of the extra traffic updates introduce. Quite often the updates sent will not be used by their recipients. This introduces extra, useless, traffic that consumes bandwidth and can ....

E. M. McCreight. The Dragon Computer System, an Early Overview. In NATO Advanced Study Institute on Microarchitecture of VLSI Computers, July 1984.

....as the processor clock speed. Switch nodes introduce a 4 cycle delay to the header of each message. In these networks contention for links and buffers is captured at the source and destination of messages. In order to keep caches coherent we used write invalidate (WI) 8] and write update (WU) [15] protocols. In the WI protocol, whenever a processor writes a data item, copies of the cache block containing the item in other processors caches are invalidated. If one of the invalidated processors later requires the same item, it will have to fetch it from the writer s cache. Our WI protocol ....

E. M. McCreight. The Dragon Computer System, an Early Overview. In NATO Advanced Study Institute on Microarchitecture of VLSI Computers, July 1984.

....this protocol, whenever a processor writes a data item, copies of the cache block containing the item in other processors caches are invalidated. If one of the invalidated processors later requires the same item, it will have to (re)fetch it from the writer s cache. Write update (WU) protocols [19] are the main alternative to invalidatebased protocols. In WU protocols, whenever an item is written, copies of the new value are sent to the other processors that share the item, so that it does not have to be (re)fetched on a later access. The tradeo between WI and WU protocols is then clear: ....

E. M. McCreight. The Dragon Computer System, an Early Overview. In NATO Advanced Study Institute on Microarchitecture of VLSI Computers, July 1984.

....In these networks contention for links and buffers is captured at the source and destination of messages. All hardware characteristics mentioned above are common in actual modern parallel architectures. In order to keep caches coherent we used write invalidate (WI) 10] write update (WU) [19] and dynamic hybrid [14] protocols. In the WI protocol, whenever a processor writes a data item, copies of the cache block containing the item in other processors caches are invalidated. If one of the invalidated processors later requires the same item, it will have to fetch it from the writer s ....

E. M. McCreight. The Dragon Computer System, an Early Overview. In NATO Advanced Study Institute on Microarchitecture of VLSI Computers, July 1984.

....In this protocol, whenever a processor writes a data item, copies of the cache block containing the item in other processors caches are invalidated. If one of the invalidated processors later requires the same item, it will have to fetch it from the writer s cache. Write update (WU) protocols [22] are the main alternative to invalidate based protocols. In WU protocols, whenever an item is written, copies of the new value are sent to the other processors that share the item. More specifically, consider the case of dependent and parallelism, where a processor A suspended on a variable and ....

E. M. McCreight. The Dragon Computer System, an Early Overview. In NATO Advanced Study Institute on Microarchitecture of VLSI Computers, July 1984.

....and uses the MINT front end, developed by Veenstra and Fowler [26] to simulate the MIPS architecture, and a back end, developed by Bianchini and Veenstra, to simulate the memory and interconnection systems. In order to keep caches coherent we used write invalidate (WI) 11] and write update (WU) [19] protocols. In the WI protocol, whenever a processor writes a data item, copies of the cache block containing the item in other processors caches are invalidated. If one of the invalidated processors later requires the same item, it will have to fetch it from the writer s cache. Our WI protocol ....

McCreight, E. M. The Dragon Computer System, an Early Overview. In NATO Advanced Study Institute on Microarchitecture of VLSI Computers (July 1984).

....and writeupdate, depending on whether a write to a replicated (shared) cache line invalidates or updates the copies, respectively. Goodman s write once [16] protocol, the Illinois [24] protocol, and directorybased protocols use write invalidate. A write update protocol was used in the Dragon [23] and Firefly [30] Previous studies have suggested that neither write invalidate (WI) nor write update (WU) outperforms the other for all applications [3, 12] In general, a WU protocol performs better than WI for programs in which the pattern of sharing is characterized by cache blocks that are ....

E. M. McCreight. The Dragon Computer System, an Early Overview. In NATO Advanced Study Insitiute on Microarchitecture of VLSI Computers, July 1984.

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