Lin Y.-L., "Recent Developments in High-Level Synthesis", ACM Trans. on Design Automation of Electronic Systems, Vol. 2, No. 1, January 1997 4, 4.2  Home/Search   Document Details and Download   Summary   Related Articles   Check

....it can operate on software, and thus algorithmic, system models and use software development tools (C compilation environments) for simulation. Algorithmic or behavioral hardware modeling introduce a higher level of design abstraction for the EDA industry. High level or behavioral synthesis [3, 9, 17], is defined as the transformation of behavioral circuit descriptions into register transfer level (RTL) structural descriptions that implement the given behavior while satisfying user defined constraints. When language based design entry is used, high level synthesis presents many similarities ....

Y.-L. Lin. Recent development in high level synthesis. ACM Transactions on Design Automation of Electronic Systems, 2(1):2--21, 1997.

....well behaved nor easily predictable under partial knowledge. This situation has worsened as technology scaled. As a result, design exploration based on behavioral synthesis has not fully met expectations, and it has found limited use in industrial design flows. The second generation of HLS tools [5, 2] has adopted a more conservative approach to ward cost metric estimation. Second generation commercial HLS tools do not claim the capability of performing constrained optimization, but they focus on the capability of synthesizing a functional designs that satisfies requirements and constraints ....

Y. Lin, "Recent Developments in High-level Synthesis," ACM Transaction on Design Automation of Electronic Systems, vol. 2, no. 1, pp. 2--21, Jan. 1997.

....tasks are very hard to solve exactly because of their combinatorial nature. For practical purposes, it is sufficient to have good enough solutions in reasonable time. Various heuristic and evolutionary algorithms have been proposed to solve these hard optimization tasks, e.g. GDW93] DMi94] Lin97] EKP98] 1.2. HLS of control dominated applications Although HLS has been successfully used in many cases, it is still not as indispensable today as layout or logic synthesis. Despite the last decade of research, there is still a long way to go before the HLS tools can compete with and exceed ....

....only of scheduling and allocation. It involves converting a system specification or a description in terms of computations and communications into a set of available system components and synthesizing these components. The main problems can be outlined as follows, in principle ( GDW93] HSE95] Lin97] BRN97] there exist a need for application specific synthesis strategies which more efficiently could cooperate with the features of a specific application domain; existing internal representations can not encapsulate details of a specification without some loss of information, therefore ....

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Y.-L. Lin, "Recent Developments in High-Level Synthesis", ACM Transactions on Design Automation of Electronic Systems, Vol. 2, No.1, pp. 2-21, Jan. 1997.

....employed since a designer may have to perform many iterations of the entire design process in a limited amount of time. These algorithms are generally fast and there has been much work in the development of good heuristics [Paulin and Knight 1989; McFarland et al. 1990; Camposano and Wolf 1991; Lin 1997]. In general these algorithms do not produce optimal solutions. Even in those cases where they produce an optimal solution, the methods do not guarantee that the solution produced is indeed optimal; so one would need to use other techniques to verify optimality. In this paper, we present an ....

....procedure Enumerate procedure UpdateASAP(i; step) for j i 1 to N do if (x j is a successor of x i ) ASAP(x j ) max(ASAP(x j ) step (x i ; x j ) endif enddo end procedure UpdateASAP Fig. 1. Na ve Complete Enumeration generic ILP solver to get the optimal schedule. See Lin [1997] for a recent survey on techniques for high level synthesis. Many di erent ILP models have been proposed [Camposano and Wolf 1991; Hwang et al. 1991] Chaudhuri and Walker [1994] and Gebotys and Elmasry [1993] have shown that ecient formulations lead to reduced execution times for the ILP ....

Lin, Y.-L. 1997. Recent developments in high-level synthesis. ACM Trans. Design Automation of Electronic Systems 2, 1 (Jan.), 2-21.

....to the way they conceive their work. However, each design must be described, eventually, at the lowest level (e.g. layout masks) in order to be fabricated. The transformation from one level of abstraction to the next is performed by various synthesis processes. High level or behavioral synthesis [11, 18, 19, 30, 31], is dened as the transformation of behavioral circuit descriptions into register transfer level (RTL) structural descriptions that implement the given behavior while satisfying user dened constraints. Today, with the adoption of standard Hardware Description Languages (HDLs) like VHDL [2, 3] or ....

Y-L. Lin. Recent development in high level synthesis. ACM Transactions on Design Automation of Electronic Systems, 2(1):221, 1997.

....In many high level synthesis systems, heuristics are employed since the designer has to perform many iterations of the entire design process in a limited amount of time. These algorithms are generally fast and there has been a lot of work in the development of good heuristics [PK89, MPC90, CW91, Lin97] Many years of research into the area of heuristic development has led to heuristics which do yield optimal solutions a considerable percentage of the time, while returning reasonable solutions in most of the other cases. However, in general these algorithms do not produce optimal solutions. 3 ....

....ILP Models In this section, ILP models for the scheduling problem are presented. Most algorithms which yield an exact (optimal) solution model the scheduling problem using Integer Linear Programming, and the ILP model is then solved using a generic ILP solver to get the optimal schedule. See Lin [Lin97] for a recent survey on techniques for high level synthesis. Many different ILP models have been proposed [CW91, HLH91, HH93a, HH93b] Chaudhuri and Walker [CW93, CW94] and Gebotys and Elmasry [GE90, GE93] have shown that efficient formulations lead to reduced execution times for the ILP ....

Youn-Long Lin. Recent developments in high-level synthesis. ACM Trans. Design Automation of Electronic Systems, 2(1):2--21, Jan. 1997.

....subsequent design steps starting with high level synthesis which is generally understood as a mapping of operations of the data flow graph to control steps and to suitable components of a given library. Even though much effort has been spent during the last years in this research area (e.g. see [10] for an overview of recent publications) the actual question of how to suitably formulate the behavioral description such that synthesis can produce efficient results has been often underrated. However, it seems obvious that even optimal synthesis algorithms can only produce results as good as the ....

Y.-L. Lin. Recent Developments in High-Level Synthesis. ACM Transactions on Design Automation of Electronic Systems, Vol. 2, No. 1, pages 2--21, 1997.

....specify a system without consideration for low level implementation details. This design style can lead to a significant reduction in a product s development cycle and cost because fewer people are needed and more design trade offs can be explored in a limited time than in a traditional work flow [19]. The counterflow pipeline is a good candidate for this type of fast, aggressive synthesis because of its extreme Automatic Design of Custom Wide Issue Counterflow Pipelines Bruce R. Childers, Jack W. Davidson Department of Computer Science University of Virginia Charlottesville, Virginia ....

Lin Y-L., "Recent developments in high-level synthesis ", ACM Trans. on Design Automation of Electronic Systems, pp. 2--21, Vol. 2, No. 1, Jan. 1997.

....at the early part of a process that involves refinement to lower level hardware and software implementations [18] A model at the system level should be expressed in a form that enables verification that a refinement correctly implements the model. Possible approaches include behavioural synthesis [32] (correct by construction) and formal verification using model checking and equivalence checking [23, 33] Refinement to a software implementation is facilitated by a system level modeling language that is closely related to programming languages. In principle, the hardware and software ....

Y.-L. Lin, "Recent Developments in High-Level Synthesis," ACM Tansactions on Design Automation of Electronic Systems, vol. 2, no. 1, pp. 2--21, 1997.

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Lin Y.-L., "Recent Developments in High-Level Synthesis", ACM Trans. on Design Automation of Electronic Systems, Vol. 2, No. 1, January 1997 4, 4.2

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Y.-L. Lin, "Recent developments in high-level synthesis," ACM Trans. Design Automat. Electron. Syst., vol. 2, no. 1, pp. 2--21, 1997.

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Lin Y. L., "Recent Development in High Level Synthesis", ACM Transactions on Design Automation of Electronic Systems, Vol 2, No 1 (January 1997), pp 2-21.

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Youn-Long Lin. Recent developments in high-level synthesis. ACM Trans. Design Automation of Electronic Systems, 2(1), pp2-21, 1997.

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Y.-L. Lin, "Recent developments in high-level synthesis," (Survey Paper), ACM Trans. Design Automation of Elec. Sys., vol. 2, no. 1, pp. 2--21, Jan. 1997.

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Y. L. Lin, "Recent Developments in High-Level Synthesis," ACM Transactions on Design Automation of Electronic Systems, vol. 2, no. 1, pp. 2--21, Jan 1997.

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