B. P. Dave, G. Lakshminarayana, N. K. Jha, "COSYN: Hardware-Software Co-Synthesis of Embedded Systems," DAC34: ACM/IEEE Design Automation Conference, pp. 703-708, Anaheim, CA, June 1997.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....optimization itself can be driven by important design objectives, such as performance, cost, and power consumption. However, most previous co design approaches have neglected issues related to power [15] 19] 23] 34] 42] or focused on distributed systems that exclude DVS processing elements [9], 13] 24] hence, leaving a major source of power reduction unexploited. Nevertheless, during the last decade power has become a main design issue of concern due to the proliferation of battery powered embedded systems which demand a cautious use of the available energy resources. One way to ....

Dave, B. P., G. Lakshminarayana, and N. K. Jha. COSYN: Hardware Software Co-Synthesis of Embedded Systems. In Proc. DAC, 1997, pp. 70308.

....crossover and mutation. MOGAC is a prototype consisting of approximately 18,000 lines of C and Bison code. Our results were obtained on a 200 MHz Pentium Pro system with 96 MB of memory running the Linux operating system. We compare our results with those of Yen [127] Hou [84] and COSYN [128], which were obtained on a SPARCstation 20, as well as those of SOS [76] which were obtained on a Solbourne Series5e 900 (similar to a SPARC 4 490) The CPU times are given in seconds. MOGAC s input consists of two ASCII files. The first file specifies the attributes of each PE, IC, and ....

....n.a. 13 13 n.a. n.a. 14 (15) 15 n.a. n.a. P P 2 6 12 12 n.a. n.a. 7 (8) 8 n.a. n.a. 10 10 10 n.a. 6 6 n.a. n.a. 5 5 5 n.a. See Figure 6.5. its run time increases dramatically with increasing problem complexity. The fourth column is for COSYN, a constructive algorithm, [128]. The fifth column is for Oh and Ha s heuristic [75] Entries of n.a. indicate that a result for the corresponding problem and optimization algorithm was not reported in the literature. The P P 2 5 entries are explained in the next few paragraphs. Prakash and Parker s examples contained no ....

[Article contains additional citation context not shown here]

B. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardware-software cosynthesis of embedded systems," in Proc. of Design Automation Conf., pp. 703-- 708, June 1997.

....of the system as a whole. The latter set of techniques can be categorized as follows. The first category consists of techniques that statically characterize the power consumption of system tasks, using simple power models for alternate implementations, and inter task communication (e.g. [14, 15]) The drawback is that they often assume statically scheduled systems, and hence do not accurately account for dynamic effects (e.g. bus conflicts, cache misses etc) The second category includes techniques based on system simulation, with power models for individual components, memories, and ....

B. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardware-software co-synthesis of embedded systems," in Proc. Design Automation Conf., pp. 703--708, June 1997.

....at the other extreme, directed, cyclic task graphs usually arise in low level or smallgrain arenas, for example, in instruction level code analysis. TGFF s task graph format, the DAG, is commonly used in medium level and high level al location and scheduling research in academia and industry [6] [8]. TGFF is nonetheless capable of generating sets of independent tasks as a special case of the sets of DAGs for which it is primarily intended. TGFF includes a pseudorandom number generator [9] This generator behaves identically on any machine which represents mantissas with 24 or more bits. ....

....indexes: tg ar[i] period = gr Delta mul ls[i] Delta p laxity Figure 1: Period computation algorithm An important characteristic of task sets is the relation between the deadlines and the periods of their task graphs. While some schedulers allow periods that are less than deadlines (e.g. 5] [8]) many do not. If requested, TGFF prevents the period of any task graph from being greater than any of the deadlines within it. In addition to the primary output file, a PostScript file depicting the task set is generated. Figure 2 shows an example task graph output by TGFF s PostScript ....

B. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardware-software co-synthesis of embedded systems," in Proc. Design Automation Conf., pp. 703--708, June 1997.

....execution. The link between co synthesis and HLS, however, has to be much stronger if fine performance trade offs between conflicting performance constraints i.e. latency and power are examined. Also, system functionality is traditionally described as a task graph with data dependencies, only [4] [8] 10] 18] This implies that co synthesis does not address any conditional behavior expressed with control dependencies. Nevertheless, handling control dependencies enables more precise performance estimations, more effective design decisions i.e. scheduling and ultimately, better quality ....

....power constraints because accurate estimations are possible only at the RTL level, hence, after HLS. A tighter integration of co synthesis and HLS is probably needed to surmount this limitation. Shin et al. [14] describe a power efficient scheduling method that exploits slack times. Dave et al. [4] propose a low power co synthesis method that includes allocation, scheduling and performance estimation. Their method is at the task level so that estimation is limited to average power. Also, authors do not consider any low power specific design issues [12] i.e. temporary shut down of unused ....

B. Dave et al, "COSYN: Hardware-Software Co-Synthesis of Embedded Systems", Proc. of DAC, 1997, pp.703-708.

....core of the Nimble Compiler is a hardware software partitioning algorithm that partitions applications onto the CPU and the datapath. As opposed to many co synthesis algorithms that work at moderate to coarse granularities (such as task level and function level) and extract task level parallelism [2][7] 10] our algorithm performs fine grain partitioning at the loop and basic block levels to exploit potential instruction level parallelism (ILP) to significantly accelerate important loops in the FPGA. There have been considerable research efforts in co design of conventional embedded ....

.... Most of the partitioning algorithms model the system based on an architectural template of a CPU (software) and an ASIC (hardware) 4] 5] 7] 11] Recent work in co synthesis has used a more generalized model consisting of heterogeneous multiprocessors with various communication topologies [2][9] 10] Although some of the above techniques use highly abstract architecture models that might be retargetable to reconfigurable architectures, none of them can represent the special characteristics of the platform such as the reconfiguration overhead or possibility of both spatial and temporal ....

B. Dave, G. Lakshminarayana, and N. Jha, "COSYN: hardware-software co-synthesis of embedded systems," Proc. 34th Design Automation Conference, 1997.

....[ HW = 0.5 R N A ( if SA [ SW = # # # mapping state , outperforms version A. 4.2 COSYN Optimal or nearly optimal hardware software cosynthesis solutions are difficult to achieve since there are numerous relevant implementation considerations and constraints. The COSYN algorithm [18], developed by Dave, Lakshminarayana, and Jha, takes numerous elements of this complexity into account. The design considerations and objectives addressed by the algorithm include allowing arbitrary, possibly heterogeneous collections of processors and communication links; intraprocessor ....

....hand, if , then an allocation is chosen from that maximizes the sum (39) of best case finish times over all actors for which deadlines exist. In both cases, the maxima over the respective sets of sums are taken because they ultimately lead to final allocations that have lower overall dollar cost [18]. 4.2.5 Accounting for power consumption A low power version of the COSYN algorithm, called COSYN LP, has been developed to minimize power consumption along with overall dollar cost. In addition to the algorithm inputs defined in Section 4.2.1, COSYN LP also employs average power dissipation ....

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B. P. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardware-Software Co-Synthesis of Embedded Systems," in Proceedings of the Design Automation Conference, 1997.

....Recently, there has been an increased interest in hardware software co design and co synthesis both in the academia and in the industry. Most hardware software compilation systems focus on the functional partitioning of designs amongst ASIC (hardware) and CPU (software) components [5][6][7] In addition to using traditional behavioral synthesis languages such as Verilog and VHDL, synthesis from software application languages such as C C or Java is also gaining popularity. Some of the systems that synthesize subsets of C C or C based languages include HardwareC [21] SystemC ....

B. Dave, G. Lakshminarayana, and N. Jha. COSYN: hardware-software cosynthesis of embedded systems, Proc. 34 th Design Automation Conference, 1997.

....offers a comprehensive solution i.e. an approach that takes into consideration the interdependency of all relevant system parts in order estimate minimize energy power dissipation of the complete system. This lack has been recognized by recent research activities in low power co synthesis [10, 11] even if these approaches do not reflect all system resources (no caches) Co synthesis driven by other constraints (performance and in parts hardware effort) has been explored by [12, 13, 14, 15] among others. The case study presented in this paper quantifies the interdependency of various ....

B.P. Dave, G. Lakshminarayana, N.K. Jha, COSYN: Hardware-Software CoSynthesis of Embedded Systems' IEEE Proc. of 34th. Design Automation Conference (DAC97), pp.703-708, 1997.

.... eenpublishedbyOngetal.whoshowedthatthepowerconsumptionmaydrasticallydependonthealgorithmdeployedforaspe cificfunctionality.Apowerandperformancesimulationtoolthat canbeusedtoconductarchitecture leveloptimizationshasbeenintroducedbySatoetal. 15] In[11]atask levelco designmethodologyisintroducedthatoptimizesforpowerconsumptionandperformance. Theinfluenceof cachesisnottakenintoconsideration.Furthermore,theprocedure fortaskallocationisbasedonestimationsforanaveragepower consumptionofanprocessingelementratherthanassuming,for ....

B.P. Dave, G. Lakshminarayana, N.K. Jha, COSYN: HardwareSoftware Co-Synthesis of Embedded Systems' IEEE Proc. of 34th. Design Automation Conference (DAC97), pp.703-708, 1997.

....consider the application of shutdown, supply voltage reduction, both shutdown and supplyvoltage reduction, and dynamically variable voltage approach, respectively. With the shutdown technique, the system will operate at Task is executed in the interval [0, 5] Task is executed in the interval [5, 10]. The processor can be shut down for the interval [10, 20] and then be resumed for the next task. The duty cycle of the processor is 50 , so the average power consumption is 0.5 W. With the supply voltage reduction technique, the system will operate at a lower but fixed supply voltage level. ....

....both shutdown and supplyvoltage reduction, and dynamically variable voltage approach, respectively. With the shutdown technique, the system will operate at Task is executed in the interval [0, 5] Task is executed in the interval [5, 10] The processor can be shut down for the interval [10, 20] and then be resumed for the next task. The duty cycle of the processor is 50 , so the average power consumption is 0.5 W. With the supply voltage reduction technique, the system will operate at a lower but fixed supply voltage level. Unfortunately, the tight deadline on Task means that the ....

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B. P. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardwaresoftware co-synthesis of embedded systems," in Proc. Design Automation Conf., 1997, pp. 703--708.

....our approach can be divided into three categories: work on system level power optimization in general, architectural power optimization focusing on a single core (like a CPU, cache, main memory, etc. and work on bus issues like power, performance, and size. As for the first group, Dave et al. [2] introduce a codesign methodology that optimizes for power and performance at the task level. Their procedure for task allocation is based on an average power consumption and does not take into consideration data dependencies on the instruction level to estimate optimize power. In addition, they ....

....data are sent over the bus [12] transition s Given the traffic on a bus, power can be quickly estimated using analytical models as described above. Likewise, similar analytical models can be applied to compute cache and memory power (and performance) These have been extensively modeled by [2]. D. Experimental Results In order to verify our approach, we performed the following experiments. We explored power and performance for mapping the diesel and ckey to our system architecture and exploring three parameterized parts: cache, CPU cache (Processor Local) bus, and cache memory ....

B. P. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardware --software co-synthesis of embedded systems," in Proc. DAC'97, 1997, pp. 703--708.

....in SPI, and since the basic Simulink concept of periodic execution is maintained for time continuous blocks, they can be mapped to SPI in the same way as blocks with a discrete sample time. Granularity The task of finding a good process granularity is important for an efficient implementation [2]. As an extension to rule 1 in section 4.1, we thus allow the designer to specify which Simulink blocks should be clustered into a single SPI process, independent of subsystems used in Simulink to build hierarchical block diagrams. This independence is useful, since subsystems in Simulink are a ....

B. P. Dave, G. Lakshminarayana, and N. K. Jha. COSYN: Hardware-software co-synthesis of embedded systems. In Proceedings 34th Design Automation Conference (DAC '97), Annaheim, USA, June 1997.

....thus underlining its usefulness as part of any system design flow. B. Related Work There is a large body of work on system level synthesis of application specific architectures through HW SW partitioning and mapping of the application tasks onto pre designed cores and application specifichardware[1,2,3,4,5,6,7,8]. Whilemost C5 C1 C3 C2 C4 C6 C7 C8 (a) Example system of communicating components Bus2 I F Bridge Bus1 I F Bus1 I F C3 C2 Bus1 I F C4 Bus1 I F Bus1 I F C1 Bus2 I F C6 Bus2 I F C7 C5 Bus2 I F C8 Bus2 I F Bus 1 Bus 2 Bus2 I F Bridge Bus1 I F Bus1 I F C3 C2 Bus1 ....

B. P. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: hardwaresoftware cosynthesis of embedded systems ," in Proc. Design Automation Conf., pp. 703--708, 1997.

.... romthedesignprocesspointofview,manyoftheembeddedsystemscanbeintegratedonjustonechip (systems onachip)usingcorebaseddesigntechniques.Previous workincore basedsystemdesignhasmainlyfocusedon performanceandcostconstraints.Somerecentworkhas beenpresentedinco synthesisforlowpower[1,2].However, thetrade offinenergydissipationamongsoftware 1 , memoryandhardwarehasnotyetbeenexplored.Thisis achallengingandindispensabletaskforthedesignoflow powerembeddedsystems.Considerforexample,thatthe useofabiggercachecanreducethenumberofcachemisses ....

B.P. Dave, G. Lakshminarayana,N.K. Jha, COSYN: Hardware-Software CoSynthesis of Embedded Systems' Proc. DAC'97, pp.703-708,1997.

....to our approach can be divided into three categories: work on system level power optimization in general, architectural power optimization focusing on a single core (like a CPU, cache, main memory etc. and work on bus issues like power, performance and size. As for the first group, Dave et al. [5] introduce a co design methodology that optimizes for power and performance at the task level. Their procedure for task allocation is based on an average power consumption and does not take into consideration data dependencies on the instruction level to estimate optimize power. In addition, they ....

B.P. Dave, G. Lakshminarayana, N.K. Jha, COSYN: Hardware-Software Co-Synthesis of Embedded Systems' Proc. DAC'97, pp.703-708, 1997.

....have started investigating system level tradeoffs and optimizations whose effects transcend the individual component boundaries. Techniques for synthesis of multiprocessor system architectures and heterogeneous distributed HW SW architectures for real time specifications were presented in [9, 10]. These approaches either assume that all tasks are pre characterized with respect to all possible implementations for delay and power consumption, or assume a significantly simplified power dissipation model. In [11] and [12] separate execution of an instruction set simulator (ISS) based ....

B. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardwaresoftware co-synthesis of embedded systems," in Proc. Design Automation Conf., pp. 703--708, June 1997.

....for debugging of the hardware software. Coarse grain partitioning algorithms often start from a task graph which consists of a set of communicating processes. In the published literature, task graphs that describe the set of communicating processes (or tasks) such as the ones shown in [4] 5] [6]) are directed acyclic graphs (DAGs) that use nodes to represent processes and arcs to Jui Ming Chang is with Hewlett Packard Laboratories, Palo Alto, CA 94304 and Massoud Pedram is with the Department of Electrical Engineering Systems, University of Southern California, Los Angeles, CA 90089. ....

B. P. Dave, G. Lakshminarayana, and N. Jha, \Cosyn: Hardware-Software Co-Synthesis of Embedded Systems," in Proceedings IEEE-ACM Design Automation Conference, 1997.

....modules contain much less of these specifications. To which level should the functionality and hardware objects be decomposed is system specific and cannot be easily decided at the beginning of the design process. A number of papers have been published which deal with the partition problem [3 5, 7, 9, 11 13]. They differ by the levels of abstractions, the target architecture, and or the search algorithms used, but these approaches have the common feature: they can only take fixed granularity of tasks and hardware modules as inputs. This might be efficient in the 1 case where the behavior of a system ....

B.Dave, G.Lakshminarayana, and N.K.Jha "COSYN:Hardware-software co-synthesis of embedded systems", Proc. Design Automation Conference, 703-798, 1997.

.... our best knowledge except some partitioning works considering diverse hardware implementations[6] 7] On the other hand, hardware software cosynthesis problem has been addressed in the DHE design where the problem size of interest is manageable with mathematical or probabilistic approach[3] 4] 8][9]. In particular, very recently Dick and Jha[10] presented a multiobjective genetic algorithm (called MOGAC) for hardware software cosynthesis of distributed embedded systems. Since they formulate the problem carefully in a genetic algorithm framework, they achieved significant enlargement of ....

....(BIL) of node i with (the largest deadline node i s deadline execution time) and take the larger as the revised priority. This modification gives higher priority to the task of earlier deadline. Table 1 compares the performance of the proposed algorithm with those of Hou s algorithm[3] COSYN[9] and MOGAC[10] when they are applied to the unclustered(u) and clustered(c) version of Hou s task graphs. Table 2 compares the performance of the proposed algorithm with those of SOS[4] COSYN and MOGAC for Prakash and Parker s task graphs[4] P P1 4 means that Prakash and Parker s first ....

B. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardware-software cosynthesis of embedded systems," in Proc. Design Automation Conf., June 1997, pp. 703-708.

....and data dependencies further complicate the problem by causing hard to predict program caching behaviors. Even without the task interactions, program level models are still too expensive to be used in design space exploration for multi tasking systems. Kirovski et:al: 7] and Dave et:al: [8] worked on system level synthesis for lowpower but did not consider memory hierarchies. In this paper, we present a new approach that can handle multiple tasks with data dependencies and simultaneously evaluates the power consumptions of CPU, cache and main memory. Our algorithm minimizes overall ....

B.P. Dave, G. Lakshminarayana, N.K. Jha, "COSYN: HardwareSoftware Co-Synthesis of Embedded Systems", in Proc. DAC'97, 1997.

.... and assigning tasks from the system specification to processors from a given candidate set to minimize power while satisfying hard real time constraints was addressed in [10] The synthesis of distributed, embedded hardware software systems under real time constraints was addressed in [6]. The above approaches either assume that all tasks are pre characterized on all available processors for delay and power consumption, or assume a significantly simplified power dissipation model (e.g. a constant power active cycle for each processor) These assumptions and simplifications are ....

B. Dave, G. Lakshminarayana, and N. K. Jha. COSYN: Hardware-software co-synthesis of embedded systems. In Proc. Design Automation Conf., pages 703--708, June 1997.

....protocols, and place our work in the context of previous work in those fields. There is a large body of work on system level synthesis of application specific architectures, through HW SW partitioning, mapping of the application tasks onto pre designed cores, and application specific hardware [1, 2, 3, 4, 5, 6, 7, 8, 9]. Those that do not ignore communication altogether either assume a fixed communication protocol (e.g. PCI based buses) or select from a communication library of a few alternative protocols. Research on system level synthesis of communication architectures [10, 11, 12, 13] mostly deals with ....

B. P. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: hardware-software cosynthesis of embedded systems ," in Proc. Design Automation Conf., pp. 703--708, 1997.

....any static customization of the protocol parameters. 1. 2 Related Work There is a large body of work on system level synthesis of application specific architectures, through HW SW partitioning, and through mapping of the application tasks onto pre designed cores and application specific hardware [1, 2, 3, 4, 5, 6, 7, 8]. Those that do not ignore communication altogether, either assume a fixed communication protocol (e.g. PCI based buses) or select from a communication library of a few alternative protocols. Research on system level synthesis of communication architectures [9, 10, 11, 12] mostly deals with ....

B. P. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: hardware-software cosynthesis of embedded systems ," in Proc. Design Automation Conf., pp. 703-- 708, 1997.

....and place our work in the context of previous work in those fields. There has been a large body of work on systemlevel synthesis of application specific architectures through HW SW partitioning and mapping of the application tasks onto pre designed cores and application specific hardware [1, 2, 3, 4, 5, 6, 7, 8, 9]. While some of these techniques attempt to consider the impact of communication effects during HW SW partitioning and mapping, they either assume a fixed communication protocol (e.g. PCI based buses) or select from a communication library of a few alternative protocols. Research on ....

B. P. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: hardware-software cosynthesis of embedded systems ," in Proc. Design Automation Conf., pp. 703--708, 1997.

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B. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardware-software co-synthesis of embedded systems," in Proc. Design Automation Conf., pp. 703--708, June 1997.

....only the local effects of these changes. This often leads to an accumulation of sub optimal decisions, especially when large systems are constructed. Despite their susceptibility to becoming trapped in local minima, constructive algorithms are capable of producing high quality results [20] [21]. However, in Srinivasan s work, power consumption is not taken into account, the communication model is simplistic, and multi rate systems are not efficiently handled [20] COSYN was the first cosynthesis system to take power consumption into account [21] Communication links are modeled and ....

.... of producing high quality results [20] 21] However, in Srinivasan s work, power consumption is not taken into account, the communication model is simplistic, and multi rate systems are not efficiently handled [20] COSYN was the first cosynthesis system to take power consumption into account [21]. Communication links are modeled and heuristics are used to tackle multi rate systems. Although fast, COSYN suffers from an inability to do true multiobjective optimization. Two types of probabilistic optimization algorithms have been applied to the co synthesis problem: simulated annealing ....

[Article contains additional citation context not shown here]

B. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardware-software co-synthesis of embedded systems," in Proc. Design Automation Conf., pp. 703--708, June 1997.

....to sacrifice the guarantee of solution optimality. Iterative improvement algorithms start with a complete solution and make local changes to it in an attempt to improve the solution s cost [5] 12] 13] Constructive algorithms build a system by incrementally adding components to it [14] [15]. Simulated annealing algorithms have been successfully used to partition hardware software systems [16] Genetic algorithms have been applied to the hardware software partitioning problem [17] A multiobjective genetic algorithm was applied to the more general co synthesis problem [18] MOCSYN, ....

B. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardwaresoftware co-synthesis of embedded systems," in Proc. Design Automation Conf., pp. 703--708, June 1997.

....which rely on optimal mixed integer linear programming [4] and exhaustive exploration [5] can only be applied to small instances of the co synthesis problem. Heuristics have seen some success with larger instances of the distributed system co synthesis problem. The constructive algorithm used in [6] was the first to target low power. However, like iterative improvement algorithms [2] 7] conventional constructive algorithms may become trapped in local minima. A genetic algorithm was previously applied to the hardware software partitioning problem [8] However, in this work only one ....

....11,550 N. A. N. A. 170 8.0 1.6 Hou 1 2 (clustered) 170 16.0 170 6.9 170 5.1 0.7 Hou 3 4 (clustered) 170 3.3 N. A. N. A. 170 2.2 0. 6 each PE and link s hyperperiod schedule, obtaining the system energy required (this includes the idle PE link energy) and dividing the energy by the hyperperiod [6]. Constraint violation: A system s constraint violations are derived from its costs and the constraints imposed by the designer. Solutions have a number of hard constraints. Although solutions in which one or more hard constraints have been violated are invalid, MOGAC treats them no differently ....

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B. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardware-software co-synthesis of embedded systems," in Proc. Design Automation Conf., pp. 703--708, June 1997.

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B. P. Dave, G. Lakshminarayana, N. K. Jha, "COSYN: Hardware-Software Co-Synthesis of Embedded Systems," DAC34: ACM/IEEE Design Automation Conference, pp. 703-708, Anaheim, CA, June 1997.

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B. Dave, G. Lakshminarayana, and N. Jha, "COSYN: Hardware-Software Co-Synthesis of Embedded Systems ", in DAC, 1997.

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B. Dave, G. Lakshminarayana and N. Jha, "COSYN: Hardware-Software Co-synthesis of Embedded Systems ", Proceedings of the 34 Design Automation Conference, pp. 703--708, June 1997.

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B. Dave, G. Lakshminarayana, and N. K. Tha, "COSYN: Hardware-software co-synthesis of embedded systems," in Proc. Design Automation Conf., June 1997, pp. 703--708.

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Dave, B.P.; Lakshminarayana, G.; Jha, N.K., "Cosyn: Hardware-software Co-synthesis Of Embedded Systems ", in Proc. 34th Design Automation Conference, 1997, Page(s): 703-708.

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B. P. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: hardwaresoftware co-synthesis of embedded systems", Proc. of the 34th DAC 1997, pp. 703-708.

No context found.

B. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardware-software cosynthesis of embedded systems," in Proc. Design Automation Conf., pp. 703--708, June 1997.

No context found.

B. P. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardwaresoftware cosynthesis of embedded systems," in Proc. DAC-34: ACM/IEEE Design Automation Conf., Anaheim, CA, June 1997, pp. 703--708.

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