R. Camposano and A. Kunzmann, "Considering timing constraints in synthesis from a behavioral description," in Proc. Int. Conf. Comput. Des., 1986, pp. 6--9.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....High level Synthesis system are presented. Keywords: control synthesis, synchronization, relative scheduling, timing constraints. Introduction We consider the synthesis of synchronous digital systems from a behavioral description that includes the specification of timing constraints [1]. We address the problem of finding a minimal area control unit implementation, such that the overall hardware is a valid implementation of its behavioral model. The minimization of the control unit area, referred to as control optimization, can be performed either at the logic level by using a ....

....assigning the following start times: T(s) T(b) T(c) 0, T(d) 3, T(e) 4. If there are no unbounded delay operations, then the concept of feasibility is sufficient to guarantee that a schedule exists. It can be shown that a graph is feasible if and only if it contains no positive length cycles [1, 10]. In the presence of unbounded delays, however, we extend the analysis. A graph is well posed if a schedule based on the start times defined above exists such that the constraints can be satisfied for all values of unbounded delays; otherwise, it is called ill posed. The graph in Figure 2(a) is ....

R. Camposano and A. Kunzmann, "Considering timing constraints in synthesis from behavioral description," in Proceedings of the International Conference on Computer Design, pp. 6-9, Nov. 1986.

....at least 5 cycles after the completion of a. 3.2 Well Posedness of Timing Constraints An important consideration during scheduling is whether a schedule exists under the required timing constraints. An analysis of the consistency of timing constraints was presented by Camposano and Kunzman in [23] for graphs with no unbounded delay operations. In this case, a schedule exists if and only if no positive cycles are present in the constraint graph, where a positive cycle is a cycle whose sum of the edge weights is a strictly positive integer [20] This condition can be checked by the ....

R. Camposano and A. Kunzmann, "Considering timing constraints in synthesis from behavioral description," in Proceedings of the International Conference on Computer Design, pp. 6-9, Nov. 1986.

....approach will be described for defining, in a safe way, minimum and maximum timing constraints in a VHDL input specification program. 2.1. Timing Definition Coherency The general problem of checking the consistency of a specification with timing constraints has been addressed, for instance, in [3] [11] 13] Instead, concerning the use of VHDL as specification language for synthesis, the problem of defining a synthesizable subset of the whole language has been addressed in [12] 9] 4] 14] 7] 8] In pure VHDL, the typical algorithmic constructs, composed by high level sequential ....

R. Camposano, A. Kunzmann, "Considering Timing Constraints in Synthesis from a Behavioral Description", Proceedings of ICCD, October 1986.

....behavioral specification submitted to the synthesis system. These constraints have to be captured as part of the internal design representation generated after compilation of the input specification. Verification of consistency and operation scheduling under timing constraints are discussed in [Camposano 86] and [Ku 92] In this paper we propose a notation for the specification of timing constraints in VHDL and discuss some aspects concerning its implementation. The definition of standard VHDL [IEEE 87] is based on the simulation cycle and considers only strict timing. This produces certain ....

....syntax to specify minimal and maximal timing constraints in HardwareC. A constraint on a sequence of statements is specified with respect to labels associated to the first respective last statement of the sequence. A similar approach is that of Camposano for the DSL hardware description language [Camposano 86] DSL syntax allows timing constraints to be specified for any statement or group of statements. VHDL has been defined as a simulation language [IEEE 87] According to its standard semantics both after clauses in signal assignment statements and wait statements with time clauses are expressing ....

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R. Camposano, A. Kunzmann, Considering Timing Constraints in Synthesis from a Behavioral Description, Proc. ICCD, 1986, 6-9.

.... have to be captured as part of the internal design representation generated after compilation of the input specification and timing analysis has to decide if the constraints are consistent and if operation scheduling according to the imposed restrictions can be performed during synthesis [Ku 92, Camposano 86] In [Eles 94b] we presented a notation for the specification of timing constraints in VHDL. The proposed notation is implemented in the VHDL front end of the CAMAD high level synthesis system designed at Linkping University [Peng 94, Eles 92] The design environment is built on top of the CAMAD ....

R. Camposano, A. Kunzmann, Considering Timing Constraints in Synthesis from a Behavioral Description, Proc. ICCD, 1986, 6-9.

....2 shows possible relations and corresponding constraint graphs. There are two important previous results that lay down the conditions for determining constraint satisfiability. The following theorem occurs in various forms in di#erent application areas. Its proof can be found in, for example, in [16, 12, 17]. Theorem 4.1 (Static scheduling) In the absence of any ND operations, a set of operation delay constraints is satisfiable if and only if there exist no positive cycles in G T . Using a relative scheduler, a minimum delay constraint is always satisfiable since from any solution that satisfies ....

R. Camposano and A. Kunzmann, "Considering Timing Constraints in Synthesis from a Behavioral Description," in Proceedings of the International Conference on Computer Design, pp. 6--9, 1986.

....in time constrained systems has often been addressed in the context of operation schedulability under given timing assumptions and processor characteristics. The following references point to literature in capturing constraints, particularly timing constraints and analysis techniques [Das85, CK86, GM94b, Lau89, Lei80, LW82, LL73] Compilation issues for hardware software systems When compiling for hardware and software from a single specification, the optimizations required use different metrics and cost criteria. The following discuss the anatomy of compilation and issues [Haa91, ....

R. Camposano and A. Kunzmann. Considering Timing Constraints in Synthesis from a Behavioral Description. In Proceedings of the International Conference on Computer Design, pages 6--9, 1986.

.... issues such as processor utilization, bus bandwidth allocation, use of application profiling information for architecture tuning and queueing analysis [6] Micro level system performance evaluation consists of analysis at the process and operation level and evaluation of the runtime system [7, 8, 9, 10, 11, 12]. We focus on process level and operation level performance analysis in this paper. ffl OPERATION LEVEL ANALYSIS is carried out on individual process level models. As such only constraints that concern within one process are considered. In addition, inter process synchronization is not considered ....

....time evolution of the the embedded system behavior in presence of inter process synchronization relationships. We illustrate the process level analysis by an example below. Example 4.3. p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 9 [2, 6] 4, 20] 3, 10] 9, 18] 10, 20] 1, 4] 4, 10] 3, 5] 3, 6] 7,20] [5, 8] SCC 1 SCC 2 Figure 3: Process graph. Consider the process graph shown in Figure 3 with the delay intervals as shown on the edges. For SCC1 , the lower bound on the execution rate is derived by setting edge delays at upper bound and computing the maximum mean weight cycle from the critical cycle ....

R. Camposano and A. Kunzmann, "Considering Timing Constraints in Synthesis from a Behavioral Description," in Proc. ICCCD, pp. 6--9, 1986.

....be captured as part of the internal design representation generated after compilation of the input specification. Timing analysis has to be carried out in order to decide if the constraints are consistent, and operation scheduling is performed during synthesis according to the imposed restrictions [8, 1, 7]. In [5] we proposed a notation for the specification of timing constraints in VHDL. We also presented solutions for synthesis of VHDL specifications with timing constraints preserving consistency between the behavior of the simulation model and that of the synthesized hardware. The proposed ....

R. Camposano and A. Kunzmann, Considering Timing Constraints in Synthesis from a Behavioral Description, in: Proc. ICCD'86, 1986, 6-9.

....and the IIT Education Research Initiative Fund. To appear in IEEE Transactions on CAD, May 1993 (Tentative) 2 the various hardware resources used during allocation. Second and equally important, it fixes the relative timing of operators and thus the satisfaction of timing constraints. [2,3]. Timing constraints are important because they allow designers to specify both desired performance and interface information [2,4] Fig. 1 illustrates the scheduling problem using a typical CDFG, which is a directed graph in which nodes represent operators and edges represent ordering ....

....types of ordering dependencies. Data edges represent the flow of data from one operator to another, implying an ordering relationship because the data must be computed before it is used. Control edges represent ordering relationships associated control operations such as conditionals. Timing edges [2,3] represent timing constraints between two operators that must be satisfied in a correct design. A timing constraint specifies the required relative timing between two operators. Minimum timing constraints specify a lower bound on the relative timing between operators, while maximum timing ....

R. Camposano and A. Kunzmann, "Considering Timing Constraints in Synthesis from a Behavioral Description", Proceedings ICCD, pp. 6-9, Oct. 1986.

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R. Camposano and A. Kunzmann, "Considering timing constraints in synthesis from a behavioral description," in Proc. Int. Conf. Comput. Des., 1986, pp. 6--9.

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