Liedtke, J., Elphinstone, K., Schonberg, S., Hartig, H., Heiser, G., Islam, N., Jaeger, T.: Achieved IPC performance. In: 6th Workshop on Hot Topics in Operating Systems (HotOS), Chatham, Massachusetts (1997)  Home/Search   Document Not in Database   Summary   Related Articles   Check

....Go s measurements were made using the Pentium s RDTSC instruction which counts the number of cycles that have elapsed since the machine was reset. The test machine was a Pentium 90 with 32 MB of RAM. Results for comparison with other systems are extracted from published benchmarks [4] papers [14, 7, 9, 11] and experimentation. All results are in machine cycles. OS hardware Null RPC Domain Transfer BSD Pentium 55,000 13,000 Mach 2.5 MIPS 3,000 1,600 Spring SPARC 880 L4 Pentium 665 121 Pebble MIPS 114 Go Pentium 85 39 Note that some of the gures in this table were obtained on di erent ....

J. Liedtke et al. Achieved ipc performance. In Proc. 6th Workshop on Hot Topics in Operating Systems (HotOS), pages 28-31, May 1998.

....5. 7 The high cost of switching between protection domains motivated the current generation of microkernels, which link server code directly into the kernel address space (e.g. Chorus [Guillemont91] Windows NT [Microsoft95] which eliminates the safety offered by isolation. The L4 microkernel [Leidke97] addresses the context switching cost directly, greatly reducing the work done by, and cost of, upcalls. L4 is discussed in more detail below. The Exokernel architecture [Engler95] follows a different path: although, as with conventional microkernels, most operating system work is done at user ....

....[McVoy96] However, there has been considerable progress made in bringing domain crossing costs down, primarily concentrating on reducing the amount of hardware and system state changed on a context switch. Perhaps the most technically impressive work has been done on Leidke s L4 microkernel [Leidke97]. By carefully laying out kernel code so that it remains in the level one cache and minimizing the work done by the kernel when changing fault domains, L4 performs hardware fault domain (address space) switches in 121 machine cycles (0.73s on a 166MHz Pentium) Leidke justifies his minimalist ....

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Leidke, J., Elphinstone, K., Schnberg, S., Hrtig, H., Heiser, G., Islam, N., Jaeger, T., "Achieved IPC Performance," Proceedings of the Sixth Workshop on Hot Topics in Operating Systems, pp. 28--31, Cape Cod, MA (May 1997).

....for an IPC. On a Pentium 200 MHz machine, 142 cycles corresponds to 0.71 microseconds. To our knowledge, the fastest IPC mechanism that exists on a Pentium is provided by the L4 microkernel. In L4, the time taken for an IPC request reply in the best case is 242 cycles on a Pentium 166 MHz machine [9]. This cycle count also assumes that all the parameters can be passed via registers. In L4, processes shares page tables as far as possible. Hence a page table switch is not required on an IPC. An IPC request reply in L4 would still involve four protection domain crossings into and from the ....

Liedtke, J.; Elphinstone, K.; Schonberg, S.; Hartig, H.; Heiser, G.; Islam, N.; Jaeger, T.; "Achieved IPC Performance", Sixth Workshop on Hot Topics in Opertaing Systems (HoTOS - VI), May 1997. BIBLIOGRAPHY 67

....for a Null function call to complete, compared to 464 secs for a more conventional RPC call. Note that two context switches and a total of four protection domain crossings into and from the kernel must still be performed by the LRPC mechanism for a request reply transaction. The L4 microkernel [8] tries to optimize the overhead associated with an IPC by sharing page tables between multiple processes. On the Intel Pentium Processor, the kernel ensures that processes are protected from each other by reloading the segment registers on a context switch. Thus a page table switch and the ....

....theoretical cycle counts is mainly due to data control pipeline hazards. To the best of our knowledge, the fastest IPC mechanism that exists on a Pentium is provided by the L4 microkernel. In L4, the time taken for an IPC request reply in the best case is 242 cycles on a Pentium 166 MHz machine [8]. This cycle count also assumes that all the parameters can be passed via registers. In L4, processes shares page tables as far as possible. Hence an IPC does not require page table switch. Still, a request reply IPC in L4 would involve four protection domain crossings, whereas Palladium takes ....

Liedtke, J.; Elphinstone, K.; Schonberg, S.; Hartig, H.; Heiser, G.; Islam, N.; Jaeger, T.; "Achieved IPC Performance", Sixth Workshop on Hot Topics in Opertaing Systems (HoTOS - VI), May 1997.

....has focused on finding and fixing the performance bottlenecks of microkernel approach, which has required rethinking its basic architecture. Liedtke, in his work on L4, has espoused the philosophy of a minimal privileged mode kernel that includes only support for IPC and key VM primitives [Liedtke97]. Pebble goes one step further than L4, removing VM as well (except for TLB fault handling, which is done in software on MIPS) The Exokernel [Kaashoek97] attempts to exterminate all OS abstractions, leaving the privileged mode kernel in charge of protecting resources, but leaving abstraction of ....

J. Liedtke et al., "Achieved IPC Performance, " Proc. 6th HotOS, pp. 28--31 (May 1998).

....into servers that a VM system should provide, and in some cases allow applications more direct access to the services that a VM system provides the kernel. Research using the L3 and L4 microkernels has been used to determine the maximal achievable level of IPC performance the hardware will allow [37, 38]. This was done by hand coding the IPC mechanism in assembly language, ensuring that code and data was positioned in memory in such a way that they all could be co resident in the cache, and by minimizing the number of TLB flushes used for an IPC operation. The result of this exercise shows that ....

J. Liedtke, K. Elphinstone, S. Schonberg, H. Hartig, H. Gernot, N. Islam, and T. Jaeger. Achieved IPC performance. In Proceedings of Hot Topics in Operating Systems (HotOS) 1997, pages 28--31, 1997.

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Liedtke, J., Elphinstone, K., Schonberg, S., Hartig, H., Heiser, G., Islam, N., Jaeger, T.: Achieved IPC performance. In: 6th Workshop on Hot Topics in Operating Systems (HotOS), Chatham, Massachusetts (1997)

No context found.

Jochen Liedtke, Kevin Elphinstone, Sebastian Schonberg, Hermann Hartig, Gernot Heiser, Nayeem Islam, and Trent Jaeger. Achieved IPC performance. In 6th Workshop on Hot Topics in Operating Systems (HotOS), Chatham, Massachusetts, May 1997.

No context found.

J. Liedtke et al. Achieved IPC Performance. In Proc. 6th Workshop on Hot Topics in Operating Systems (HotOS), pages 28-31, May 1998.

No context found.

J. Liedtke, K. Elphinstone, S. Schonberg, H. Hartig, G. Heiser, N. Islam, and T. Jaeger, "Achieved IPC performance," in Proc. 6th Workshop on Hot Topics in Operating Systems (HOTOS '97), pp. 28--31, May 1997.

No context found.

J. Liedtke, K. Elphinstone, S. Schoenberg, and H. Haertig. Achieved IPC performance. In IEEE, editor, The Sixth Workshop on Hot Topics in Operating Systems: May 5--6, 1997.

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