A. Curiger, H. Bonnenberg, R. Zimmermann, N. Felber, H. Kaeslin, and W. Fichtner, "VINCI: VLSI implementation of the new secret-key block cipher IDEA," in Proc. IEEE Custom Integrated Circuits Conf., pp. 15.5.1--15.5.4, May 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....architecture result in large improvements in performance as well as energy efficiency. However, space restrictions dictate that the discussions in this paper be limited to performance issues. Algorithm specific custom hardware implementations can always provide the highest levels of efficiency [10, 11, 12, 13]. However, in practice, the need for efficiency in security processing has to often be considered together with, and traded off against, the need for flexibility. Each security protocol standard typically specifies a wide range of cryptographic algorithms that the network servers and clients need ....

A. Curiger, H. Bonnenberg, R. Zimmermann, N. Felber, H. Kaeslin, and W. Fichtner, "VINCI: VLSI implementation of the new secret-key block cipher IDEA," in Proc. IEEE Custom Integrated Circuits Conf., pp. 15.5.1--15.5.4, May 1993.

....of IDEA was developed and verified by Bonnenberg et al. in 1992 using a 1.5 m CMOS technology [10] This implementation had an encryption rate of 44 Mb sec. In 1994, VINCI, a 177 Mb sec VLSI implementation of the IDEA algorithm in 1. 2 m CMOS technology, was reported by Curiger et al. [11, 12]. A 355 Mb sec implementation in 0.8 m technology of IDEA was reported in 1995 by Wolter et al. 13] Tradeoffs in Parallel and Serial Implementations of IDEA 3 followed by a 424 Mb sec single chip implementation of 0.7 m technology by Salomao et al. 14] was reported. In 2000, Leong et al. ....

A. Curiger, H. Bonnenberg, R. Zimmerman, N. Felber, H. Kaeslin, and W. Fichtner, "VINCI: VLSI implementation of the new secret-key block cipher IDEA," in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 15.5.1--15.5.4, 1993.

....patterns, as shown in Figure 6. We refer to the first pattern (shown in Figure 6(a) as point to point. In this pattern, each logic subcircuit pin connects to exactly one data pin in one memory block Example circuits that employ this pattern can be found in [8] 9] 10] 11] 7] 8] 12] [13], 14] 15] 16] 17] 18] 19] 20] We refer to the pattern shown in Figure 6(b) as shared connection pattern. A typical use of such a pattern is described in [21] in which the data in ports of a scratch pad memory and first in first out buffer are connected to a bus. Other examples can ....

A. Curiger, H. Bonnenberg, R. Zimmerman, N. Felber, H. Kaeslin, and W. Fichtner, "Vinci: VLSI implementation of the new secret-key block cipher idea," in Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, pp. 15.5.1--15.5.4, May 1993.

....implementation of IDEA was developed and verified by Bonnenberg et al. in 1992 using a 1:5 m CMOS technology [9] This implementation had an encryption rate of 44Mb sec. In 1994, VINCI, a 177Mb sec VLSI implementation of the IDEA algorithm in 1:2 m CMOS technology, was reported by Curiger et al. [10, 11]. A 355Mb sec implementation in 0:8 m technology of IDEA was reported in 1995 by Wolter et al. 12] The fastest single chip implementation of which we are aware is a 424Mb sec implementation of 0:7 m technology by Salomao et al. 13] A commercial implementation of IDEA called the IDEACrypt ....

A. Curiger, H. Bonnenberg, R. Zimmerman, N. Felber, H. Kaeslin, and W. Fichtner, "VINCI: VLSI implementation of the new secret--key block cipher IDEA," in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 15.5.1-- 15.5.4, 1993.

....logic subcircuits drive at least one pin of each memory. An example of this pattern can be found in [46] where input data is appended with a time stamp as it is put into FIFOs. The same patterns are common in the data out network. Examples of the single logic single memory pattern can be found in [42, 43, 47, 48, 49]. Examples of the multiple logic single memory pattern can be found in [50, 51] Examples of the single logic multiple memory pattern are described in [7, 4, 43, 46, 52] Finally, examples of the multiple logic multiple memory pattern can be found in [53] Logic Subcircuit Logical Memory Logical ....

A. Curiger, H. Bonnenberg, R. Zimmerman, N. Felber, H. Kaeslin, and W. Fichtner, "Vinci: VLSI implementation of the new secret-key block cipher idea," in Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, pp. 15.5.1--15.5.4, May 1993.

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A. Curiger, H. Bonnenberg, R. Zimmermann, N. Felber, H. Kaeslin, W. Fichtner, VINCI: VLSI Implementation of the New Secret-Key Block Cipher IDEA, IEEE Custom Integrated Circuits Conference, 1993.

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