E. Girczyc and J. Knight, "An ADA to standard cell hardware compiler based on grammars and scheduling," in Proceedings of the International Conference on Computer Design, pp. 726-731, Oct. 1984.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... Some systems perform module binding before scheduling, e.g. Caddy DSL [2] and BUD [3] some systems perform scheduling before module binding, e.g. Facet [4] DAA [5] YSC [6] HIS [7] Combined heuristic scheduling and binding are performed in other synthesis systems, such as MAHA [8] ELF [9], Slicer Splicer [10] Chippe [11] Hal [12] and Genie S [13] It is important to remark that most of these approaches assume that each module is characterized a priori in terms of area and execution time. We consider in this paper the scheduling problem for the high level synthesis of digital ....

E. Girczyc and J. Knight, "An ADA to standard cell hardware compiler based on grammars and scheduling," in Proceedings of the International Conference on Computer Design, pp. 726-731, Oct. 1984.

....by exact methods, it is necessary to employ heuristic algorithms. Extensive research has been performed in this area during the last two decades; many heuristic schedulers have been developed, e.g. force directed schedulers [5] topological permutation schedulers [4] and list schedulers [3], to name a few. Lately, research has also been focused on constraint analysis techniques. These techniques decrease the apparent scheduling freedom, without removing any feasible schedules. This means that the search space of the scheduler is reduced, while the solution space is left unaltered. ....

G.F. Girczyc and J.P. Knight. An ADA to Standard Cell Hardware Compiler Based on Graph Grammars and Scheduling. Proc. Int. Conf. on Computer Design, pp. 726--731, 1984.

....arc represents the data dependency between two nodes. One of main tasks in the high level synthesis is scheduling. In the scheduling task, each node of the given CDFG is assigned to a control step under timing or area constraints. Most scheduling algorithms including MAHA [1] SLICER [2] Elf [3], and FDS [4] are based on various heuristics respectively so as to reduce their run time at the price of producing non optimal scheduling results sometimes. Also, an Integer Linear Programming (ILP) approach which always yields an optimal scheduling result is used in ALPS [5] In this approach, a ....

E. F. Girczyc and J. P. Knight, "An ADA to Standard Cell Hardware Compiler based on Graph Grammar and Scheduling", Proc. ICCD-84, pp.726-731, October 1984.

....type checking. Moreover, some optimizing transformations may be done at this stage, such as expression simplification. These graphs are given different names in different synthesis systems (e.g. value trace [46] data dependency graph [2] directed acyclic graph [14] control and data flow graph [17]) but are simply different adaptations of similar basic concept. In many systems, the control and data flow graphs are integrated into one structure. In this paper we will use the term flow graph. Before proceeding to the second step it is desirable to do some initial optimization of the flow ....

....[27] The scheduling and allocation are closely interrelated. In order to have an optimal design, both tasks should be performed simultaneously [19] However, due to the time complexity, many systems perform them separately [10,22,26,29,47,49] or introduce iteration loops between the two subtasks [17,32,34,44]. Scheduling involves assigning the operation to so called control steps. A control step is the fundamental sequencing unit in synchronous systems; it corresponds to a clock cycle. Different methods for scheduling will be examined in detail in the following sections. Allocation involves ....

[Article contains additional citation context not shown here]

Girczyc E. F. and Knight J. P. (1984) An ADA to Standard Cell Hardware Compiler Based on Graph Grammars and Scheduling. Proc IEEE Int'l Conf. Computer Design, p. 726-731.

....approaches such as simulated annealing, and exact approaches such as integer linear programming. Greedy heuristics attempt to minimize resource costs but do not guarantee that an optimal schedule will be found. Examples of greedy approaches include fast, simple heuristics such as list scheduling [8, 9, 10, 11, 12] and more complex (and more effective) heuristics such as force directed scheduling [5] Greedy heuristics suffer the shortcoming that they can be trapped in local minima in the cost function and so may not find the globally best schedule. Transformational approaches alter an existing schedule ....

....especially as schedule length is increased for a given CDFG. To appear in IEEE Transactions on CAD, May 1993 (Tentative) 4 Only a few scheduling approaches attempt to meet arbitrary timing constraints while minimizing resource costs. Constructive heuristics include modified list scheduling [9,2] heuristics that attempt to meet timing constraints during scheduling, and force directed scheduling, which uses local timing constraints [5] to limit the time frames of control steps into which an operator may be scheduled. In another approach, timing constraints have been included in an ILP ....

[Article contains additional citation context not shown here]

E. Girczyc and J. Knight, "An ADA to standard cell hardware compiler based on graph grammars and scheduling," in Proceedings ICCD, pp. 726-731, Oct. 1984.

....controllers. Taking into account earlier control constraints on the high level synthesis process (such as control part area, number of control signals) would make possible a greater optimization of the control part. Integrating control considerations into data path synthesis comes back to ELF [6]. In this system, the optimization algorithm, which is based on graph grammar, uses a cost function with a control signals complexity measure to estimate control overhead, but only in terms of control interconnection complexity and estimate too roughly the real cost of the final control part ....

E.F. Girczyc and J.P. Knight. An ada to standard cell hardware compiler based on graph grammars and scheduling. In Proc. of ICCD, pages 726--731, 1984.

No context found.

E.F. Girczyc and J.P. Knight. An Ada to Standard Cell Hardware Compiler Based on Graph Grammars and Scheduling. In Proc. of ICCD-84, pp. 726-731. IEEE, Port Chester, NY, Oct., 1984.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC