J.-G. Chung and K. K. Parhi, "Pipelining of Lattice IIR Digital Filters," IEEE Trans. Signal Processing, vol. SP42, pp. 751--761, Apr. 1994. 21  Home/Search Document Not in Database Summary Related Articles Check |
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Algorithm-Based Low-Power Transform Coding Architectures - Part.. - Wu, Liu (1995) (Correct)
....C eff Delta V 2 dd Delta f clk ; 28) Algorithm Based Low Powe Transform Coding Architectures Part I 9 where C eff is the effective loading capacity, V dd is the supply voltage, and f clk is the operating frequency. Also, the lowest possible supply voltage V 0 dd can be approximated by [1][13] V 0 dd (V 0 dd Gamma V t ) 2 = M V dd (V dd Gamma V t ) 2 ; 29) where M is the decimation factor and V t is the threshold voltage of the device. Assume that V dd = 5V , V t = 0:7V in the original system. For the 16 point Chebyshev IDCT under normal operation, it requires 18 ....
J.-G. Chung and K. K. Parhi, "Pipelining of lattice IIR digital filters," IEEE Trans. Signal Processing, vol. 42, pp. 751--761, April 1994.
Determining the Minimum Iteration Period of an Algorithm - Ito, Parhi (1995) (9 citations) Self-citation (Parhi) (Correct)
....This graph consists of only 9 nodes, 18 edges, and 10 delays. 7 Experimental Results The CPU time to determine the iteration bound for practical SRDFGs are compared. We chose the 5th order elliptic wave filter (EWF) 14] and the recursive part of the 4 level pipelined lattice filter (PLF) [15] as benchmarks. EWF which consists of 34 nodes, 56 edges, and 7 delays is an SRDFG where the number of delays, jDj, is relatively smaller than the number of nodes, jN j, and the number of edges, jEj. On the other hand, PLF which consists of 8 nodes, 10 edges, and 8 delays is an SRDFG where jDj is ....
J.-G. Chung and K. K. Parhi, "Pipelining of Lattice IIR Digital Filters," IEEE Trans. Signal Processing, vol. SP42, pp. 751--761, Apr. 1994. 21
Determining the Iteration Bounds of Single-Rate and Multi-Rate .. - Kazuhito Ito (1994) (2 citations) Self-citation (Parhi) (Correct)
....This graph consists of only 9 nodes, 18 edges, and 10 delays. 6 Experimental Results The CPU time to determine the iteration bound for practical SRDFGs are compared. We chose the 5th order elliptic wave filter (EWF) 11] and the recursive part of the 4 level pipelined lattice filter (PLF) [12] as benchmarks. EWF which consists Table IComp arisonof IterationBound DeterminationAlgorithms CPU [mS] Method Time complexity Memory requirement EWF PLF NCD O(jN jjEj log jN j) O(jN j jEj) 25.2 a 1.00 c LPM O(jDjjEj jDj 3 log jDj) O(jN j jDj 2 ) 3.58 a 6.38 c MCM O(jDjjEj ....
J.-G. Chung and K. K. Parhi, "Pipelining of Lattice IIR Digital Filters," IEEE Trans. Sgnal Processing, vol. SP-42, pp. 751--761, Apr. 1994.
Determining the Minimum Iteration Period of an Algorithm - Ito (1995) (9 citations) Self-citation (Parhi) (Correct)
....This graph consists of only 9 nodes, 18 edges, and 10 delays. 7. Experimental Results The CPU time to determine the iteration bound for practical SRDFGs are compared. We chose the 5th order elliptic wave filter (EWF) 14] and the recursive part of the 4 level pipelined lattice filter (PLF) [15] as benchmarks. EWF which consists of 34 nodes, 56 edges, and 7 delays is an SRDFG where the number of delays, jDj, is relatively smaller than the number of nodes, jN j, and the number of edges, jEj. On the other hand, PLF which consists of 8 nodes, 10 edges, and 8 delays is an SRDFG where jDj is ....
J.-G. Chung and K. K. Parhi, "Pipelining of Lattice IIR Digital Filters," IEEE Trans. Signal Processing, vol. SP-42, pp. 751--
ILP Based Cost-Optimal DSP Synthesis with Module Selection.. - Ito, Lucke, Parhi (1999) (3 citations) Self-citation (Parhi) (Correct)
....are prepared for each data format f since the constraints (10) 12) are applied to each data format f 2 FORM. Example: In Table III we compare the solution of the time assignment models with and without (w o) schedule range folding for synthesizing the 4 stage pipelined lattice filter from [42] using the libraries of processors and converters of Tables I and II in section VII. We synthesize this DFG using the three time assignment models discussed in the next section. The table contains the number of constraints, the number of variables, and the CPU times in seconds for the ILP models. ....
....architecture. Therefore, reducing the pool of processors by the first model and minimizing the converter cost by the third model can generate the optimal or a very near optimal architecture. Example: The three models and the original model are applied to the the 4 level pipelined lattice filter [42]. Table IV compares the intermediate results of the three step ILP solution versus the complete ILP solution. Table IV shows the synthesized architecture; the cost of the architecture; the number of constraints; the number of integer variables in each ILP model; and the CPU time (in seconds) to ....
J.-G. Chung and K. K. Parhi, "Pipelining of lattice IIR digital filters," IEEE Trans. Signal Processing, vol. SP-42, no. 4, pp. 751--761, Apr. 1994.
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