T. Isshiki and W. Dai. High-level bit-serial datapath synthesis for multi-FPGA systems. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 167--173, Monterey, CA, February 1996. Home/Search Document Details and Download
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Adaptive Explicitly Parallel Instruction Computing - Talla (2000) (4 citations) (Correct)
....is gaining momentum. 3. 2 Application Studies Wireless communications, spread spectrum communications,IQ demodulation [102, 142, 82] Genetic Algorithms [54, 68, 151, 97, 56, 55] SAR,ATR [127, 130, 126, 167] Image coding, compression [147, 49, 142, 1, 16, 170, 134, 37, 41, 18] DCT,FFT,filters [148, 35, 176, 115, 81, 116, 146, 89]. Viterbi decoder [180] Parallel object recognition, geometric hashing [ Digit recurrence division, square root [100, 99] Various (big num, algebra, 23 etc) 16] Polynomial evaluations [44] On line arithmetic [160] Floating point arithmetic [46] CORDIC [6, 104] Character recognition ....
T. Isshiki and W. Dai. High-level bit-serial datapath synthesis for multi-FPGA systems. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 167--173, Monterey, CA, February 1996.
Reconfigurable Architectures and General-Purpose Computing in the.. - DeHon (1996) (Correct)
....1 PE, 11 cycles 4.8 Vector (w 16 Theta16 mpy) ABI 95] 16 Theta16 8 per cycle 82 FPGA [ATT94] 8 Theta8 27 PLCs, 19ns 30 [Alt96] 8 Theta8 164 LEs, 49ns 8.6 [LE94] 8 Theta8 66 CLBs, 102ns 7. 6 16 Theta16 102 CLBs, 152ns 13 32 Theta32 174 CLBs, 254ns 18.5 200 Theta200 930 CLBs, 1320ns 26 [ID95] 16 Theta16 316 CLBs, 26ns 25 [ID95] 16 Theta16 88 CLBs, 120ns 19 PADDI2 [YR95] 16 Theta8 4 PEs, 50MHz 150 MATRIX 8 Theta8 1 BFU, 20 ns 110 16 Theta16 6 BFU, 20 ns 74 Table 29: Survey of Programmable Multiply Capacity Table 28 shows a few, sample, semicustom multiplier implementations. At 330 and ....
....16 Theta16 mpy) ABI 95] 16 Theta16 8 per cycle 82 FPGA [ATT94] 8 Theta8 27 PLCs, 19ns 30 [Alt96] 8 Theta8 164 LEs, 49ns 8.6 [LE94] 8 Theta8 66 CLBs, 102ns 7. 6 16 Theta16 102 CLBs, 152ns 13 32 Theta32 174 CLBs, 254ns 18.5 200 Theta200 930 CLBs, 1320ns 26 [ID95] 16 Theta16 316 CLBs, 26ns 25 [ID95] 16 Theta16 88 CLBs, 120ns 19 PADDI2 [YR95] 16 Theta8 4 PEs, 50MHz 150 MATRIX 8 Theta8 1 BFU, 20 ns 110 16 Theta16 6 BFU, 20 ns 74 Table 29: Survey of Programmable Multiply Capacity Table 28 shows a few, sample, semicustom multiplier implementations. At 330 and 560 MPY Bit Ops= 2 s, the gate ....
Tsuyoshi Isshiki and Wayne Wei-Ming Dai. High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems. In Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 167--173. ACM, February 1995.
Reconfigurable Architectures for General-Purpose Computing - DeHon (1996) (55 citations) (Correct)
....1 PE, 11 cycles 4.8 Vector (w 16 Theta16 mpy) ABI 95] 16 Theta16 8 per cycle 82 FPGA [ATT94] 8 Theta8 27 PLCs, 19ns 30 [Alt96] 8 Theta8 164 LEs, 49ns 8.6 [LE94] 8 Theta8 66 CLBs, 102ns 7. 6 16 Theta16 102 CLBs, 152ns 13 32 Theta32 174 CLBs, 254ns 18.5 200 Theta200 930 CLBs, 1320ns 26 [ID95] 16 Theta16 316 CLBs, 26ns 25 [ID95] 16 Theta16 88 CLBs, 120ns 19 PADDI2 [YR95] 16 Theta8 4 PEs, 50MHz 150 MATRIX 8 Theta8 1 BFU, 20 ns 110 16 Theta16 6 BFU, 20 ns 74 Table 5.3: Survey of Programmable Multiply Capacity 5.3 General Purpose Multiply Implementations For comparison, Table 5.3 ....
....16 Theta16 mpy) ABI 95] 16 Theta16 8 per cycle 82 FPGA [ATT94] 8 Theta8 27 PLCs, 19ns 30 [Alt96] 8 Theta8 164 LEs, 49ns 8.6 [LE94] 8 Theta8 66 CLBs, 102ns 7. 6 16 Theta16 102 CLBs, 152ns 13 32 Theta32 174 CLBs, 254ns 18.5 200 Theta200 930 CLBs, 1320ns 26 [ID95] 16 Theta16 316 CLBs, 26ns 25 [ID95] 16 Theta16 88 CLBs, 120ns 19 PADDI2 [YR95] 16 Theta8 4 PEs, 50MHz 150 MATRIX 8 Theta8 1 BFU, 20 ns 110 16 Theta16 6 BFU, 20 ns 74 Table 5.3: Survey of Programmable Multiply Capacity 5.3 General Purpose Multiply Implementations For comparison, Table 5.3 summarizes the capacity density of several ....
Tsuyoshi Isshiki and Wayne Wei-Ming Dai. High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems. In Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 167--173. ACM, February 1995.
Software Technologies for Reconfigurable Systems - Hauck, Agarwal (1996) (2 citations) (Correct)
....to create hardware implementations the translation software faces a mapping process more complex than for standard hardware description languages. There have been many research projects that have developed methods for translating code in C [Athanas93, Wazlowski93, Agarwal94, Wo94, Galloway95, Isshiki95, Peterson96, Clark96, Yamauchi96] C [Iseli95] Ada [Dossis94] Occam [Page91, Luk94] data parallel C [Gokhale93, Guccione93] Smalltalk [Pottier96] Assembly [Razdan94a, Razdan94b] or other special hardware description languages [Singh95, Brown96] into FPGA realizations. These systems ....
T. Isshiki, W. W.-M. Dai, "High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pp. 167-173, 1995.
A Universal Pezaris Array Multiplier Generator for SRAM-Based.. - Stohmann, Barke (1997) (Correct)
.... Pezaris multiplier onto XC3000 architecture AND 2 AND FA LUT CLB Library Cell AND FA (1) FA (2) FA (1) AND FA (2) 8 by 8 Multiplier IMS [Pet95] FComp A 63 (15) 64 74 (22) C 126 (15) 150 32 by 32 Multiplier IMS [Fan96] A 1023 (63) 1910 B 1023 (63) 1022 16 by 16 Multiplier IMS [Pet95] FComp [Iss95]#1 [Iss95]#2 A 255 (31) 259 295 (33) 263 368 C 510 (31) 535 Table 5. Comparison of different multipliers. XC4000 (A) XC3000 (B) and Flex8000 (C) We have compared the implementation results produced by our approach to several recently published approaches. Array multipliers of 8, 16 ....
.... multiplier onto XC3000 architecture AND 2 AND FA LUT CLB Library Cell AND FA (1) FA (2) FA (1) AND FA (2) 8 by 8 Multiplier IMS [Pet95] FComp A 63 (15) 64 74 (22) C 126 (15) 150 32 by 32 Multiplier IMS [Fan96] A 1023 (63) 1910 B 1023 (63) 1022 16 by 16 Multiplier IMS [Pet95] FComp [Iss95]#1 [Iss95]#2 A 255 (31) 259 295 (33) 263 368 C 510 (31) 535 Table 5. Comparison of different multipliers. XC4000 (A) XC3000 (B) and Flex8000 (C) We have compared the implementation results produced by our approach to several recently published approaches. Array multipliers of 8, 16 and 32 bit ....
[Article contains additional citation context not shown here]
T. Isshiki, W. W.-M. Dai: "High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems", FPGA '95, pp. 167-173
FPGA-Based Digit-Serial CSD FIR Filter For Image Signal.. - Lee, Chung, Sobelman (Correct)
....are: limited routing resources, limited I O resources and large routing delays. Under these circumstances, a bit serial approach [3] has been more suited to mapping onto FPGAs than a bit parallel approach. The effectiveness of the bit serial architectures on FPGAs was described by Isshiki [4] and bit serial CSD FIR filters have been proposed by He [5] and Turner [6] Although the bit serial architecture is areaefficient, the time efficiency is not as good. In practical DSP applications, it may be desirable to combine the area efficiency of a bit serial architecture with the ....
T. Isshiki and W. W. Dai, "High-level bit-serial datapath synthesis for multi-FPGA systems," Proc. of ACM Third International Symposium on Field Programmable Gate Arrays, pp. 167-173, 1995.
Fpga-Based Fir Filters Using Digit-Serial Arithmetic - Hanho Lee (1997) (2 citations) (Correct)
....limited routing resources, limited I O resources and large routing delays. Under these circumstances, a bit serial approach [4] has been more suited to mapping onto FPGAs than a bit parallel approach. The effectiveness of bit serial architectures on FPGAs was described by Turner [3] and Isshiki [6]. This research was supported by Defense Advanced Research Project Agency under contract number DA DABT6396 C 0050. Although the bit serial architecture is area efficient, the time efficiency is not as good. In practical DSP applications, it may be desirable to combine the areaefficiency of a ....
T. Isshiki and W. W. Dai, "High-level bitserial datapath synthesis for multi-FPGA systems, " 1995 ACM Third International Symposium on Field Programmable Gate Arrays, pp. 167-173, 1995.
Comparing Computing Machines - DeHon (1998) (4 citations) (Correct)
....Area and Time 16 Theta16 8 Theta8 Size ( mpy 2 s scale 2 s mpy 2 s scale 2 s Custom 16 Theta16 [11] 0.63 m 2.6M 2 , 40 ns 9.6 9.6 9.6 9.6 Custom 8 Theta8 [33] 0.80 m 3.3M, 4.3 ns 70 70 Gate Array 16 Theta16 [5] 0.75 m 26M, 30ns 1.3 1.3 1.3 1.3 FPGA XC4K [36] 0.60 m 1. 25M 2 CLB [17] 316 CLBs, 26 ns 0.097 [7] 84 CLBs, 40 ns 0.24 [8] 220 CLBs, 12.1 ns 0.30 [7] 22 CLBs, 25 ns 1.5 16b DSP [18] 0.65 m 350M 2 , 50 ns 0.057 0.057 0.057 0.057 RISC [37] 0.75 m 125M 2 , 66 ns cycle (no multiplier) 22] two 16b operands 44 cycles 0.0028 16b constant 7 cycles 0.017 one 8b ....
Tsuyoshi Isshiki and Wayne Wei-Ming Dai. HighLevel Bit-Serial Datapath Synthesis for Multi-FPGA Systems. In Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 167--173. ACM, February 1995. Preliminary Copy Contact author <amd@cs.berkeley.edu> for final.
High-Performance Bit-Serial Datapath Implementation for.. - Isshiki (1996) (1 citation) Self-citation (Isshiki) (Correct)
No context found.
T. Isshiki and W. W. -M. Dai, "High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems," Proc. ACM/SIGDA Int. Symp. Field Programmable Gate Arrays, Feb. 1995.
Adaptive Explicitly Parallel Instruction Computing - Surendranath Talla Of (2000) (4 citations) (Correct)
No context found.
T. Isshiki and W. Dai. High-level bit-serial datapath synthesis for multi-FPGA systems. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 167--173, Monterey, CA, February 1996.
Comparing Computing Machines - DeHon (1998) (4 citations) (Correct)
No context found.
T. Isshiki and W. W.-M. Dai, "High-level bit-serial datapath synthesis for multi-fpga systems," in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 167--173, ACM, February 1995.
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