R. W. Brodersen, (ed.), "Anatomy of a Silicon Compiler", Klewer Academic Publishers, 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....is shown in Fig. 3. The temperature sensor [8] digital filter [12] and TMIC are indicated on the photo. The TMIC occupies 231.3 pm X 1094.4 pm of the area and contains 3293 transistors. The layout of the TMIC was generated by Powerview schematic capture tools [13] and Lager synthesis tools [14] using standard cells developed for the ERIF chip. These standard cells have been modified previously to fit sub micron processes. Functionality of the TMIC was verified by Powerview simulations using Lager standard cell VHDL models and Berkeley IRSIM [15] at the transistor switch level. Both ....

R.W. Brodersen, Anatomy of a Silicon Compiler, 1992.

....with lower cost are obtained. Techniques presented in [14 and 19] can be used for changing the implementation suggestion. 3. 2 Related work Several design systems for VLSI design based on the concept of transformational design exist or are under construction as part of larger projects (e.g. HYPER [20, 12, 21, 22], CAMAD [23, 24] SynGuide [25, 18] GATE [14] Yorktown [26] ESPRIT FORMAT[27] however most of them are restricted to optimizations at a single abstraction level (algebraic, loop, common subexpression elimination, retiming and scheduling transformations) some, such as GATE and HYPER, include ....

R.W. Brodersen, et al, Anatomy of a Silicon Compiler, Kluwer, ISBN 0-79239249-3, 1992.

....path of a 13 bit adder to 3 times the carry path of a 13 bit adder, leading to a reduced number of pipeline stages thereby further reducing the area. The timing is illustrated in figures 1.4 and 1. 6 where a simple carry propagation timing model is used to estimate the latency of the circuit [Bro92 Chapter 16, page 231]. The gray areas indicate components with fixed latencies while the diagonal lines indicate components with a latency that depends linearly on the word length. Closely spaced diagonal lines indicate parallel carry ripple paths. The speed of the circuit could be improved even more by using a ....

....are very important because they allow for the efficient mapping to hardware and reduction of the number of operation kinds which is essential for the application of common subexpression elimination and sharing transformations. These classes of transformations are missing in the Hyper system [Bro92, Cha92 and Pot94] and the CAMAD system [Pen89, Pen94] and only partially used in [Jan94] 1994 P.F.A. Middelhoek University of Twente 18 Transformation New Primitive Uses Comment algebraic 7 associativity n y 1 distributivity n y 1 commutativity n y 1 identity n y 2 (inverse) self inverse n y 2 strength ....

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R.W. Brodersen, et al, Anatomy of a Silicon Compiler, Kluwer, ISBN 0-79239249-3, 1992

....of such systems include the Cathedral compilers developed at IMEC [DeM86] the commercial DSP Station, and the Piramid [WBM90] and Phideo [LMW91, LMV94] compilers from Philips Research. Such systems use application specific specification languages, most notably the applicative language Silage [Hil85, Bro92] as used for DSP applications. In industry, however, there is a demand to standardize on languages such as VHDL. In existing systems achieving correct implementations is often based on the assumption that by automating synthesis less errors will be made. This is probably true, although ....

....design systems have been developed in recent years both for software and hardware design. In this paper we give a short list of references to work in the hardware domain. A more complete discussion can be found in [MiR96] The HYPER system developed at the University of Berkeley [Bro92, Cha92, IPS93, Pot94, CPM95] provides a set of automatic algorithmic level design optimization. Within the context of HYPER automatic optimization scripts have been developed for different purposes, including optimizing resource utilization, critical path and power reduction, and to improving testability. Transformations in ....

R.W. Brodersen, et al, Anatomy of a Silicon Compiler, Editor R.W. Broderson, Kluwer, ISBN 0-79239249-3, 1992.

....and is timeconsuming. Furthermore the efficiency and real time requirements are also very stringent compared to most software. Many (partially) transformation based design systems exist or are under construction as part of larger projects. The HYPER system developed at the University of Berkeley [Bro92, Cha92, IPS93, Pot94] provides a set of transformations for automatic algorithmic level design optimization. HYPER consists of transformations from the optimization, refinement, time space assignment categories. The refinement transformations are however limited to strength reduction. Silage is ....

R.W. Brodersen, et al, Anatomy of a Silicon Compiler, Kluwer, ISBN 0-79239249-3, 1992.

.... comparison between the designs obtained using behavioral synthesis tools and designs that are done manually [4, 6, 12] 3 Evaluation Strategy Experimental Set Up For synthesis and algorithm space exploration we used the HYPER behavioral synthesis system [10] and the LAGER silicon compiler [3], from UC Berkeley. We coded all DCT algorithms in the applicative, functional programming language SILAGE. Following an initial functional simulation, HYPER synthesizes the targeted design under the user specified set of timing throughput constraints [10] The synthesis procedure includes several ....

R. W. Brodersen, editor. Anatomy of a Silicon Compiler, Kluwer, 1992.

....or device level analysis tools (such as PowerMill [13] and SPICE [14] can be used to validate the results of the higher level tools. In order to support the design flow down to this low level of abstraction our CAD framework has been seamlessly linked to the Lager IV silicon compilation system [30]. 2.4 Summary To review, the methodology proposed in this section advocates a top down approach to design optimization. Beginning at the algorithm level, the designer can invoke behavioral power estimators to begin to classify alternative algorithms in terms of intrinsic power requirements. ATP ....

R. Brodersen, ed., "Anatomy of a Silicon Compiler," Kluwer, Boston, 1993.

....and simulations) as a function of supply voltage. Figure lb ,shows a plot of experimentally derived normalized delay vs. Van. Once again, the delay dependence on supply voltage was verified to be relatively independent of various logic functions and logic styles [1] 1.00 0.90 0.811 0.711 o. 611 0.50 0.411 0.311 0.20 O. 1C o.oCl.oo i I I I 2.00 3.00 4.00 5.00 Vdd Figure 1: Plot of normalized energy vs.Vad (la) and delay vs. Vad (lb) It is clear that operating at the lowest possible voltage is most desirable, however, this comes at the cost of increased delays and thus ....

....and the amount of extra transitions is reduced. The capacitance switched for a chained implementation is a factor of 1.5 larger than the tree implementation for a four input addition and 2.5 larger for an eight input addition. The above simulations were done on layouts generated from the LagerIV [6] compiler using the IRSIM [7] switch level simulator over 1000 random input patterns. A B U A C. Chain vs. Tree Figure 5: Reducing the glitchin activity. 3.6 Wordlength Reduction The used number of bits strongly affects all key parameters of a design, including speed, area and power. It is ....

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R. W. Brodersen, (ed.), "Anatomy of a Silicon Compiler", Klewer Academic Publishers. 1992.

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R. W. Brodersen, (ed.), "Anatomy of a Silicon Compiler", Klewer Academic Publishers, 1992.

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R.W. Brodersen, "Anatomy of a Silicon Compiler", Kluwer Academic Publishers, Chapter 18, 1992.

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