Bhasker, J. and Lee, H. "An Optimizer for Hardware Synthesis," IEEE Design and Test of Computers, pp. 20--36, October 1990. Home/Search Document Not in Database Summary Related Articles Check |
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Transformations Supporting Interactive Rescheduling for.. - Roger Ang And (1992) (Correct)
.... i ) s(v j ) D2) 6 9v k j v k is a definition of the same name variable and v k is in a node on the path (i.e. successor(s(v i ) s(v k ) and successor(s(v k ) s(v j ) 3 Related Work Similar application of compiler optimizations to tasks in high level synthesis has been done before [BhLe90] [Camp90] Walk82] but differ from this work in the design models and approach. Interactive use of similar transformations for sequential circuit behavior, retiming, has been done by [PoRa91] and [MSBS91] However, retiming differs fundamentally from rescheduling in the underlying data being ....
Bhasker, J. and Lee, H. "An Optimizer for Hardware Synthesis," IEEE Design and Test of Computers, pp. 20--36, October 1990.
Recent Developments in High-Level Synthesis - Lin (1997) (15 citations) (Correct)
....a reduction in the number of array accesses decreases the overhead resulting from accessing memory structures [42] Certain compiler transformations are specific to the HDL used for describing the design. For example, when VHDL is used for design description, several approaches proposed by [4] can identify specific syntactic constructs and replace them with attributes on signals and nets to indicate their functions. Furthermore, in order to reduce the syntactic variation of descriptions with the same semantic, Chaiyakul et al. 8] proposed a transformation technique using an ....
J. Bhasker and H-C Lee, "An Optimizer for Hardware Synthesis," IEEE Design and Test of Computers, pp. 20-36, October 1990.
An Adaptable Environment for Improved High-Level Synthesis - Öberg (1996) (1 citation) (Correct)
....The BUD system [MFKo 91] encapsulates design information on layout level in order to improve the design. Cathedral [VRBGM 93] uses a rule base for type selection and a user defined set of rules in design scripts for setting synthesis constraints. Most papers on how to perform High Level Synthesis [BhLe 90] MFPC 90] PaKn 89] and to do design optimisation using transformations presented the resent years, for instance [CPMRB 95] PoRa 94] describe how to use general purpose scheduling algorithms and optimisation transformations on a general description respectively. The general purpose synthesis ....
J. Bhasker and Huan-Chih Lee, "An optimizer for Hardware Synthesis ", IEEE Design & Test of Computers, October 1990.
A Synthesis Framework for Automatic Transformation and.. - Erik Stoy (Correct)
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Bhasker, J. and Lee, H.-C., An Optimizer for Hardware Synthesis, IEEE Design & Test of Computers, Vol. 7, No. 5, Oct. 1990, pp. 20-36
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