| D. C.-M. Chi, "Improving upon local search heuristics for VLSI standard cell placement," M.S. thesis, Comput. Sci. Dept., Univ. California, Los Angeles, CA, 1995. |
....solution quality can make or break a design. The sheer difficulty of finding good solutions increases the cost of those solutions, thus there is more interest in protecting them. 2) High quality solutions in system level and physical design often have strong structural resemblance to each other [15]. Therefore, it is challenging to devise a watermarking technique that can dramatically decrease the number of solutions without compromising solution quality. 3) With deep submicrometer technology, many performance constraints (e.g. budgeted edge delays consistent with path timing bounds) ....
....of assumed routing topology, layer usage, etc. at the level of global routing. 11 This has been generally characterized as a big valley [5] or massif central [33] the phenomenon has also been specifically documented for standard cell placements under the minimum wirelength objective [15]. A. Context for Watermarking The following ingredients form the context for a nonintrusive watermarking procedure. 1) An optimization problem with known difficult complexity, corresponding to some design synthesis task. By difficult, we mean that either achieving an acceptable solution or ....
D. C.-M. Chi, "Improving upon local search heuristics for VLSI standard cell placement," M.S. thesis, Comput. Sci. Dept., Univ. California, Los Angeles, CA, 1995.
....physical design phase for several reasons. ffl Physical design is traditionally viewed as a difficult domain, where even a small percentage variation in solution quality can make or break a design, and where high quality solutions are known to have strong structural resemblance to each other [4]. Devising a watermarking technique that can make a solution unique , without compromising solution quality, is quite challenging in such a domain. ffl With deep submicron technology, many performance constraints (e.g. budgeted edge delays consistent with path timing bounds) cannot be ....
....when a global path delay constraint is broken up into separate edge delay constraints. 5 This has been generally characterized as a big valley [3] or massif central [6] the phenomenon has also been specifically documented for standard cell placements under the minimum wirelength objective [4]. 3 Watermarking Standard Cell Place and Route We have considered a variety of mechanisms by which standardcell physical design can be constrained. Our goal has been to develop a watermarking protocol that, beyond satisfying criteria listed above, is (i) consistent with existing design practices ....
D. C.-M. Chi, Improving Upon Local Search Heuristics for VLSI Standard Cell Placement, M.S. Thesis, UCLA Computer Science Department, 1995.
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