J. Crawford. The i486 CPU: Executing instructions in one clock cycle. IEEE Micro, 10:27--36, January 1990. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Integrated Predicated and Speculative Execution in .. - August, Connors.. (1998) (36 citations) (Correct)
....better performance than each individual technique could alone provide. 1. Introduction The performance of modern processors is increasingly dependent on their ability to execute multiple instructions per cycle. While mainstream microprocessors in 1990 executed at most one instruction per cycle [5][7] those in 1995 had the ability to execute up to four instructions per cycle [6] By the year 2000, hardware technology will be capable of producing microprocessors that execute up to sixteen instructions per clock cycle. Such rapid, dramatic increases in hardware parallelism have placed ....
J. H. Crawford. The i486 CPU: Executing instructions in one clock cycle. IEEE Micro, pages 27--36, February 1990.
Latency Tolerant Architectures - Bennett (1998) (2 citations) (Correct)
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J. Crawford. The i486 CPU: Executing instructions in one clock cycle. IEEE Micro, 10:27--36, January 1990.
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