A. Hemani, B. Svantesson, P. Ellervee, A. Postula, J. berg, A. Jantsch, H. Tenhunen, "Trade-offs in High-level Synthesis of Telecommunication Systems". Workshop on Synthesis And System Integration of Mixed Technologies (SASIMI'95), pp.65-72, Nara, Japan, Aug. 1995. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
A Generic Scheme for Communication Representation and.. - Meincke, Jantsch.. (1999) Self-citation (Hemani Ellervee Jantsch Tenhunen) (Correct)
....and synthesis are used, each tailored to the efficient support of particular aspects of the system design process. Every research laboratory has developed some specific methodology to deal with the diversity issues. At the core of those methodologies is always an Internal Representation (IR) [7, 8]. The uppermost priority for an IR is to preserve the semantics of the original specification in any language [5, 6] The necessity to attain a semantically complete representation from an external design language calls for generic mapping schemes. A generic mapping scheme advises a consistent ....
A. Hemani, B. Svantesson, P. Ellervee, A. Postula, J. berg, A. Jantsch, H. Tenhunen, "Trade-offs in High-level Synthesis of Telecommunication Systems". Workshop on Synthesis And System Integration of Mixed Technologies (SASIMI'95), pp.65-72, Nara, Japan, Aug. 1995.
IRSYD - An Internal representation for System.. - Ellervee, Kumar.. (1997) Self-citation (Hemani Svantesson Ellervee Jantsch) (Correct)
....machine charts, to name some of them. Electronic System Design Lab Wed. Aug. 20, 1997 8 report irsyd 970702 v0.1.0.fr 3. IRSYD Concepts IRSYD is based on XFC (eXtended Flow Chart) 11] an internal representation used in the high level synthesis of Control and Memory Intensive SysTems (CMIST) [12, 13] for its semantics. The basic idea in IRSYD (as in XFC) is to have a representation in which it should be possible to express control flow and data flow in an integrated graph representation. In this section, we describe IRSYD concepts and how they handle various requirements of system ....
....e.g. the parts may be located in different files. 3. 2 Execution Model Control flow in a process is described by Flow Chart [9] like representation based on an earlier similar representation XFC (Extended Flow Chart [11] used in the high level synthesis of Control and Memory Intensive Systems [12, 13]. A process is a directed cyclic graph G= V,E) The nodes give control blocks and the arcs represent the precedence relationship among these nodes. To represent various situations, there are seven types of nodes, namely entry, exit, operation, condition, split, join and activate. Every process ....
Ahmed Hemani, Bengt Svantesson, Peeter Ellervee, Adam Postula, Axel Jantsch, and Hannu Tenhunen, "Trade-offs in High-level Synthesis of Telecommunication Circuits", Proceedings of SASIMI'95, Japan, 1995.
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