Blumrich et al, "Two virtual Memory Mapped Network Interface Designs", Hot Interconnects 94  Home/Search   Document Details and Download   Summary   Related Articles   Check

....single chip for full duplex 155Mbps ATM local area networks. DART permits high performance both high bandwidth and low latency via hardware that supports direct, protected, application access to the network. While such operating system bypass techniques have been implemented in prototypes [1,3,5] (sometimes for special purpose networks) or in firmware using expensive NIC cards [12] to our knowledge DART is the first commercial application of this technique to a NIC chip for mainstream LANs. The one way latency for a small message from application to application is 11sec without a switch ....

....4 banks of DRAM memory with all necessary control logic and also 4 banks of SRAM and or general external devices. 2 Direct Application Access There has been much research work documenting the overhead of conventional kernel based network interfaces and investigating OS bypass techniques (e.g. [1,5,10]) The simple design of conventional network interface hardware forces kernel demultiplexing, kernel calls, and heavyweight software interfaces (a one size fits all approach) To support high bandwidth, low overhead, and application specific protocols, DART allows an application to bypass the OS ....

Blumrich et al, "Two virtual Memory Mapped Network Interface Designs", Hot Interconnects 94

....compared the messaging support in TMC CM 5 and Cray T3D and concluded that requiring processor involvement for message reception can significantly degrade performance. I improve upon their work by exposing and examining the design space of data transfer and buffering parameters. Blumrich, et al. [14] compared the SHRIMP I and SHRIMP II NIs, but did not explore alternate data transfer and buffering mechanisms. Mackenzie, et al. 73] studied the effect of buffering using a synthetic workload and concluded that buffering messages in virtual memory can occur only rarely for realistic ....

Mattias A. Blumrich, Cezary Dubnicki, Edward W. Felten, Kai Li, and Malena R. Mesarina. Two Virtual Memory Mapped Network Interface Designs. In Hot Interconnects II, 1994.

....to the new active message system, it is often a challenge to specify fully and to define clearly a communications system (particularly one under development) such that readers will understand its various nuances. 6. 1 Princeton s SHRIMP multicomputer The Princeton SHRIMP Multicomputer [33] [34] uses reflective memory as a communications resource. The idea behind reflective memory is to establish associations between virtual memory regions in different processes and on different processors. Once setup, stores into local pages of reflective memory are automatically published to the ....

M. Blumrich, C. Dubnicki, E. Felten, K. Li and M. Mesarina, "Two Virtual Memory Mapped Network Interface Designs", In Proceedings of Hot Interconnects II, August 1994.

....containing the pointer func and the 4 integer arguments to dest. func(arg1,arg2,arg3,arg4) is invoked at dest upon arrival. JAM n( JAM reply n( dest, func, arg[ size Sends an active message containing the pointer func and up to 20 integer arguments from arg[ to dest. func(arg[0] arg[1], arg[n 1] is invoked at dest upon arrival. Block Data Transfer Primitives primitive argument description JAM xfer 4( JAM reply xfer 4( dest, seg addr, word0, word1, word2, word3 Transfers 4 integer data to dest. The transfer segment ID and address at the destination are encoded in seg ....

....and the remainder of the computer system continues to widen. Meanwhile, the network interface design for a practical NOW system must work within the limitations of existing system constraints, such as the bias for normal memory accesses versus I O accesses. The SHRIMP multicomputer project[1, 2] specifies another memory based interface to achieve low communication overhead in a stock workstation environment. The SHRIMP network interface is designed for a network of Pentium PCs with Xpress Bus and EISA Bus. Communication between any two PCs is logically an uni directional mapping of a ....

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M. A. Blumrich, C. Dubnicki, E. W. Felten, K. Li, and M. R. Mesarina. Two virtual memory mapped network interface designs. In Proceedings of Hot Interconnects II, August 1994.

....compared the messaging support in TMC CM 5 and Cray T3D and concluded that requiring processor involvement for message reception can significantly degrade performance. We improve upon their work by exposing and examining the design space of data transfer and buffering parameters. Blumrich, et al. [3] compared the SHRIMP I and SHRIMP II NIs, but did not explore alternate data transfer and buffering mechanisms. Mackenzie, et al. 25] studied the effect of buffering using a synthetic workload and concluded that buffering messages in virtual memory can occur only rarely for realistic ....

Mattias A. Blumrich, Cezary Dubnicki, Edward W. Felten, Kai Li, and Malena R. Mesarina. Two Virtual Memory Mapped Network Interface Designs. In Hot Interconnects II, 1994.

....the data block size to be larger than 64 KBytes. The overhead is the dominating factor which limits the utilization of DMA devices for fine grained data transfers. This paper describes a protected, user level DMA mechanism (UDMA) developed at Princeton University as part of the SHRIMP project [4]. The UDMA mechanism uses virtual memory mapping to allow user processes to start DMA operations via a pair of ordinary load and store instructions. UDMA uses the existing virtual memory mechanisms address translation and permission checking to provide the same degree of protection as the ....

M. Blumrich, C. Dubnicki, E. W. Felten, K. Li, and M. R. Mesarina. Two virtual memory mapped network interface designs. In Proceedings of Hot Interconnects II Symposium, pages 134--142, August 1994.

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