B.C. Brock and W.A. Hunt. A Formal Introduction to a Simple HDL. In Formal Methods for VLSI Design, J. Staunstrup, Ed., Elsevier Science Publishers B.V. (North-Holland), 1990, pp. 285-329.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....can explore the design space and generate a functionally correct design [13] Correctness is guaranteed by enforcing that all transformations in the system are verified correct in the Boyer Moore system. Brock and Hunt have used the Boyer Moore system to build correct by proof circuit generators [11]. Chin and Gordon have done some work using the HOL proof assistant. Chin [18] has used higher order logic and a functional language to verify design procedures which correctly synthesise generic arithmetic circuits. Gordon [33, 32] has used HOL and window inference for transforming ....

B. C. Brock and J. Warren A. Hunt. A Formal Introduction to a Simple HDL. In [87], chapter 7, pages 285--329.

....processor independently of the other and of the model of asynchrony. Consider send. It is the formal specification of the kernel of the send side of a microprocessor s communications module. Indeed, its definition was developed with that use in mind. See[Moo92b] Using the Formal HDL described in[BH90], it is possible to design a circuit that implements send. The formal semantics of the A Formal Model of Asynchronous Communication 29 HDL is cast as an Nqthm interpreter (or simulator) that determines the signals on all the pins and the state produced by a described design, given the initial ....

....then used Nqthm to prove the correctness of the interactive convergence clock synchronization algorithm, essentially following in the footsteps of Rushby and von Henke[RvH89] Meanwhile, the present author used the hardware description language formalized in Nqthm by B. Brock and W. Hunt[BH90] of CLI to implement the processor specified by Bevier and Young and to prove that the described design meets their specification[Moo92b] The clear but unstated direction of the CLI work on fault tolerance was to enable the eventual fabrication of a device implementing the Byzantine agreement ....

Brock, B.C. and Hunt, W.A.: A formal introduction to a simple hdl. In J. Staunstrup, editor, Formal Methods for VLSI Design, pp. 285--329. Elsevier Science Publishers B.V. (North-Holland), 1990.

....0 and 5, other components of the state are modified. The last two cycles (6 and 7) are no ops. 3 Our job is to construct a Formal HDL description of a module that implements this function and to prove that we did so. The Formal HDL we use is the descendant of that described by Brock and Hunt in [3]. At the time of this writing, the new Formal HDL has not yet been documented though we explain it briefly here. The language is connected to the hardware design tools of LSI Logic, Inc. via a Lisp program that translates Formal HDL descriptions into LSI Logic s Netlist Description Language ....

B.C. Brock and W.A. Hunt. A Formal Introduction to a Simple HDL. In Formal Methods for VLSI Design, J. Staunstrup, Ed., Elsevier Science Publishers B.V. (North-Holland), 1990, pp. 285-329.

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B.C. Brock and W.A. Hunt. A Formal Introduction to a Simple HDL. In Formal Methods for VLSI Design, J. Staunstrup, Ed., Elsevier Science Publishers B.V. (North-Holland), 1990, pp. 285-329.

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