Randall T. White. Bounding Worst-Case Data Cache Performance. PhD thesis, Florida State University, April 1, 1997.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....the compiler couldn t automatically determine. In the next step the analyzer constructs a timing analysis tree and the worst case cache performance is estimated for each loop in the tree. After these steps the user can request timing information about parts, functions or loops in the program. In [Whi97, WMH # 97] direct mapped data cache memories were included into the model. The approach works on optimized code and exploits both temporal and spatial locality. Limitations in the method still concern recursion and indirect calls. The four instruction cache categories can be used for scalar ....

Randall T. White. Bounding Worst-Case Data Cache Performance. PhD thesis, Florida State University, April 1, 1997.

....that will constrain the possible executions and make sure that there is a connection to the CFG graph created in Section 4. ffl Explain why a data cache analysis is more complicated than a instruction cache analysis. Use the code below as an illustrative example. For hints see [LMW96] or [Whi97] while(i 100000) sum = array[i] Discussion (To think about) ffl How shall caches with other replacement strategies be modelled, e.g. random ffl How shall several layered caches (with maybe different cache policies and access times) be modelled ffl How can you calculate the data ....

R. White. Bounding Worst-Case Data Cache Performance. PhD thesis, Florida State University, May 1997. Available at: http://www.cs.fsu.edu/~whalley/research.html.

.... E ects Analyses In addition to instruction cache analysis other hardware features that can be analyzed include data caches, uni ed caches, translation lookaside bu ers, dynamic branch predictions and dynamic speculative executions [HP96] Data cache analysis has been proposed in [WMH 97, Whi97] 6 . The results can typically be formulated as every i :th execution of an instruction will generate a data cache miss . As an illustration consider the example program in Figure 3 on page 5. Assuming that we have an 8 word data cache line and no con ict between A[i] and the other data items ....

Randall T. White. Bounding Worst-Case Data Cache Performance. PhD thesis, Florida State University, 1997. URL: http://www.cs.fsu.edu/~whalley/- papers/white diss97.ps.

....0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1 2 3 4 5 6 7 8 t [sec] Associativity Figure 7: Performance Overhead of Static Cache Simulation 7 Future Work The current implementation of the static cache simulator handles instruction caches. Current work is under way to handle data caching as well [21]. The data flow for set associative data caches should be handled similarly to the methods presented in this paper. The current implementation of tools only supports non recursive programs. This constraint could be lifted within the framework of the static cache simulator by bounding the recursion ....

R. White, D. B. Whalley, and M. G. Harmon. Bounding worst-case data cache performance. In IEEE Real-Time Systems Symposium, December 1996. (submitted).

....in this paper, in order to simplify the examples for the reader. 2 . r[27] r[18] LO[ A] # 7. add l2, lo( A) i3 r[28] r[20] LO[ B] # 8. add l4, lo( B) i4 r[24] 204 r[28] # 9. add i4,204, i0 r[24] r[24] 200; # 10. add i0,200, i0 r[29] r[28] 200; # 11. add i4,200, i5 r[29] r[29] r[26]; # 12. add i5, i2, i5 r[14] SV[r[14] 96] # 1. save sp, 96) sp r[20] HI[ B] # 2. sethi hi( B) l4 r[18] HI[ A] # 3. sethi hi( A) l2 r[25] 204; # 4. mov 204, i1 r[26] HI[10200] # 5. sethi hi(10200) i2 r[26] r[26] LO[10200] # 6. add i2, lo(10200) i2 r[20] 4 r[25] # 13. add ....

....# 9. add i4,204, i0 r[24] r[24] 200; # 10. add i0,200, i0 r[29] r[28] 200; # 11. add i4,200, i5 r[29] r[29] r[26] # 12. add i5, i2, i5 r[14] SV[r[14] 96] # 1. save sp, 96) sp r[20] HI[ B] # 2. sethi hi( B) l4 r[18] HI[ A] # 3. sethi hi( A) l2 r[25] 204; # 4. mov 204, i1 r[26]=HI[10200] # 5. sethi hi(10200) i2 r[26] r[26] LO[10200] # 6. add i2, lo(10200) i2 r[20] 4 r[25] # 13. add i1,4, l4 r[20] r[20] r[28] # 14. add l4, i4, l4 r[21] r[25] r[27] # 15. add i1, i3, l5 r[22] r[25] r[28] # 16. add i1, i4, l6 r[21] r[21] r[22] # 17. sub l5, l6, l5 ....

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R. White. Bounding Worst-Case Data Cache Performance. PhD thesis, Dept. of Computer Science, Florida State University, April 1997.

.... output state(B) data lines(conflicts with) ELSE output state(B) data lines(D could conflict with) calc output state(B) data lines(D could access) calc output state(B) data lines(D could conflict with) Figure 3: Algorithm to Calculate Data Cache States from fully optimized code see [16]. 3.2. Calculation of Virtual Addresses Calculating addresses that are relative to the beginning of a global variable or an activation record is accomplished within the compiler since much of the data flow information required for this analysis is readily available due to its use in compiler ....

.... 100; i ) main( char c[100] short s[100] int k[100] int i, sum; sum = 0; if ( i 3) 1) sum = k[i] c[i] else sum = s[i] Path B: Blocks 2, 4, 5 Path A: Blocks 2,3, 5 Paths in the loop: load of s[i] load of c[i] load of k[i] r[8] B[r[17] 24) 24; # 16. ldsb [ l1] o0 r[9] R[r[16]] # 17. ld [ l0] o1 r[9] r[9] r[8] # 18. add o1, o0, o1 PC=L17; # 19. ba L17 r[12] r[12] r[9] # 20. add o4, o1, o4 r[8] W[r[7] 16) 16; # 21. ldsh [ g7] o0 r[12] r[12] r[8] # 22. add o4, o0, o4 Instructions 1 through 11 Instructions 12 through 15 Block 1 Block 2 Block 3 Block 4 ....

R. White. Bounding Worst-Case Data Cache Performance. PhD dissertation, Dept. of Computer Science, Florida State University, April 1997.

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