D. Burger, "System-Level Implications of Processor-Memory Integration," Technical Report CS-TR-1997-1349, Univ. of Wisconsin, Madison, June 1997. Home/Search Document Details and Download
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Efficient SoC Design with Homogeneous Processor Arrays - Tasi (2001) (Correct)
....processor and memory on a single chip [7] Current application specific integrated circuits (ASICs) provide the possibility for mixing memory and logic processes on the same chip. Many SoC projects and studies have been done in the past few years to show benefits of system scale integration [8, 9]. Most of the studies have been dealing with vector processors or small scale MIMD processor systems. The two well known projects are IRAM (Intelligent RAM) 10] and CRAM (Computational RAM) 11] These projects may mark the real start of different parallel SoC systems, indeed also systolic ....
D. Burger, "System-Level Implications of Processor-Memory Integration", 24 th ISCA, June 1997.
Design Parameters for Distributed PIM Memory Systems - Murphy (2000) (Correct)
....digital assistants, and other devices requiring processing power and small amounts of memory could benefit tremendously from this type of system, even if one only considers the potential advantages in power consumption. Other, such as members of the Galileo group at the University of Wisconsin [5, 7, 6] see PIM as having tremendous potential for use in standard workstations. The on chip memory macro becomes either a part of the memory hierarchy, or when the memory density becomes high enough, the entire memory hierarchy. Both of these views see PIM as a technology which fits very definitely into ....
Doug Burger. System-Level Implications of Processor-Memory Integration. Proceedings of the 24th International Symposium on Computer Architecture, June, 1997.
Design Parameters for Distributed PIM Memory Systems - Murphy (2000) (Correct)
....digital assistants, and other devices requiring processing power and small amounts of memory could benefit tremendously from this type of system, even if one only considers the potential advantages in power consumption. Other, such as members of the Galileo group at the University of Wisconsin [5, 7, 6] see PIM as having tremendous potential for use in standard workstations. The on chip memory macro becomes either a part of the memory hierarchy, or when the memory density becomes high enough, the entire memory hierarchy. Both of these views see PIM as a technology which fits very definitely into ....
Doug Burger. System-Level Implications of Processor-Memory Integration. Proceedings of the 24th International Symposium on Computer Architecture, June, 1997.
Future Directions - Morgan Kaufmann Is (Correct)
....chip, even though processors are getting quite complicated. This trend is Future Directions 860 DRAFT: Parallel Computer Architecture 9 4 97 made even more clear by Figure 12 3, which shows the fraction of the transistors devoted to caches in several microprocessors over the past decade[Burg97]. The vast majority of the real estate, and an even larger fraction of the transistors, are used for data storage and organized as multiple level of on chip caches. This investment in on chip storage is necessary because of the time to access to off chip memory, i.e. the latency of chip ....
Doug Burger, System-Level Implications of Processor-Memory Integration, Workshop on Mixing Logic and DRAM: Chips that Compute and Remember at ISCA97, June 1997.
Impact of Computing-in-Memory on the Performance.. - Figueiredo.. (1998) (1 citation) (Correct)
....for novel computer organizations within the next 10 years. In particular, the increasing gap between CPU cycle times and memory access latency has motivated several proposals for either bringing the processor to the (DRAM) memory [5, 24, 23, 19] or bringing the memory (SRAM) to the processor [3]. The main purpose of the proposed designs is to avoid the so called memory wall [30, 7, 18] as well as the memory bandwidth wall [20] An HPAM also relies on computing in memory in order to avoid long memory access latencies. The analogy to memory hierarchy is present in two forms. One, ....
D. Burger. System-Level Implications of Processor-Memory Integration. In Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, ISCA'97, June 1997.
Design and Optimization of Large Size and - Low Overhead Off-Chip (Correct)
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D. Burger, "System-Level Implications of Processor-Memory Integration," Technical Report CS-TR-1997-1349, Univ. of Wisconsin, Madison, June 1997.
Characterizing a New Class of Threads in Scientific .. - Rodrigues, Murphy, .. (Correct)
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D. Burger. System-Level Implications of Processor-Memory Integration. Proceedings of the 24th International Symposium on Computer Architecture, June, 1997.
Trading Bandwidth for Latency: Managing Continuations through.. - Murphy, Kogge (2002) (Correct)
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Doug Burger. System-Level Implications of Processor-Memory Integration. Proceedings of the 24th International Symposium on Computer Architecture, June, 1997.
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