N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. Journal of Real-Time Systems, 5:319--343, October  Home/Search   Document Details and Download   Summary   Related Articles   Check

....designer to budget enough processing power to handle worst case computational requirements and safely meet deadlines under any circumstance. Sophisticated timing analyzers can calculate safe, tight WCET bounds for tasks executing on single issue inorder pipelines with instruction and data caches [2,11,12,14,15,16,17,18,26,34,42]. However, the level of sophistication needed to safely and accurately analyze more complex architectures is formidable. Currently, there is no way to precisely specify microarchitectures with a full complement of high performance techniques (complex dynamic branch predictors, caches, deep ....

....a dedicated processor. Over the past decade, various research groups have investigated static approaches for bounding WCET of realtime programs. Static analysis has been extended from unoptimized programs on simple CISC processors [10,29,30,33] to optimized programs on pipelined RISC processors [12,18,42], and from uncached architectures to architectures with instruction caches [2,14,16,26] and data caches [11,15,17,34] Lundqvist and Stenstrom modified an architectural simulator to determine WCET bounds by considering alternate execution paths in parallel (instead of following a trace) combined ....

N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. Real-Time Systems, 5(4):319--343, Oct. 1993.

....a reliable foundation block for the system. Second, the simple architecture makes the incorporation of fault tolerance such as hardware redundancy easier. Third, this simplicity offers ease of modeling for WCET analysis. It is worth noting that even simple pipelining is quite difficult to model [32]. The same reasoning provides the rationale behind disabling caches. However, it is our belief that more complex architectural features such as multiple out of order instruction issue or multithreading will trickle down to processors used in real time systems and offer more research ....

N. Zhang, A. Burns, M. Nicholson, "Pipelined Processors and WorstCase Execution Times", Journal of Real-Time Systems, Vol. 5, pp. 31934.

....real time systems relies on #######knowledge of the worst case execution time (WCET) of hard real time tasks to check if the deadline of a task can be met. A safe upper bound on the WCET of a task can be provided through static analysis, dynamic analysis or even a combination of both techniques [34, 30, 15, 41, 24, 16, 1, 22, 23, 9, 29, 38]. Regardless of the methods utilized to obtain the WCET of tasks, experiments show a wide variation between longest and shortest execution times for manyembedded applications. In [38] execution times of real world embedded tasks vary by as much as 87 relative to their measured WCET. Speci ....

N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. ######### #######, 5(4):319-343, October 1993.

....to a pessimistic schedulability analysis that results in underutilization of system resources. To obtain accurate prediction for modem highperformance processors, the timing effect of advanced architectural features should be taken into account. For example, several groups including Zhang et al. [15], Lim et al. 11] Li et al. 10] and Healy et al. 4] had investigated the prediction techniques for pipelined processors. However, most of existing techniques assume that processors can issue at most one instruction at each cycle, thus cannot produce accurate analysis results for modem ....

N. Zhang, A. Burns, and M. Nicholson. Pipelined Processors and Worst-Case Execution Times. Real-Time Systems, 5(4):31934.

....retargetable to various architectures. On the other hand, neither approach dresses the problem of predicting architecture specific timing behavior due to the various latencies inherent in memory hierarchies and pipelines. New results have begun to account for this timing variance. Zhang et al. [40] presented a timing analyzer based on a mathematical model of the pipelined Intel 80C188 processor. This analysis method is able to take into account the overlap between instruction execution and fetching, which is an improvement over schemes where instruction executions are treated individually. ....

N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. The Journal of Real-Time Systems, 5(4), October 1993. 32

.... in put(P, m) and input(Q, x) as well as a 20ms deadline between the events generated by input(P, m) and output(R, y) Meanwhile, the bracketed 20ms denotes that the un observable statement S requires a maximum of 20ms to execute, a bound obtained by a timing analysis tool (e.g. [11, 18, 24, 25, 29]) Consequently, the program possesses an inherent conflict, since S requires 20ms to execute while it is only allowed 10ms. We address this problem by an approach we call feasible code synthesis. In our example this would involve decomposing S and, if possible, moving instructions not dependent ....

N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. The Jourtal of Real-Time Systems, 5(4), October 1993. 32

....of the overall problem into sub problems, in order to handle complexity. In appendix A.1 it is shown how client server systems can be handled in the context of this thesis. Most of the recent work in the field of static timing analysis of real time programs focusses on the impact of pipelining [91, 44] and caching [67, 65] strategies. Though these are also imported problems, the new approach presented in this chapter emphasises the false path problem. However, the effects of pipelines and caches are included based on the computation times of the basic blocks, which is outlined in Subsection ....

N. Zhang, A. Burns, and M. Nicholson. Pipelined Processors and Worst Case Execution Times. Journal of Real-Time Systems, 5(4), October

....to a pessimistic schedulability analysis that results in underutilization of system resources. To obtain accurate prediction for modern highperformance processors, the timing effect of advanced architectural features should be taken into account. For example, several groups including Zhang et al.[15], Lim et al. 11] Li et al. 10] and Healy et al. 4] had investigated the prediction techniques for pipelined processors. However, most of existing techniques assume that processors can issue at most one instruction at each cycle, thus cannot produce accurate analysis results for modern ....

N. Zhang, A. Burns, and M. Nicholson. Pipelined Processors and Worst-Case Execution Times. Real-Time Systems, 5(4):319--343, Oct. 1993.

....the data references are unknown. In the past few years, research in the static analysis of WCET of programs has increased. Conventional methods for static analysis have been extended from unoptimized programs on simple CISC processors [7, 22, 21] to optimized programs on pipelined RISC processors [9, 17, 28] and from uncached architectures to instruction caches [3, 11, 15] However, there has been little previous work on predicting WCET for data caching. Only three previous attempts have been reported. Rawat and Nilsen [23] used a graph coloring approach to bound data caching performance. However, ....

N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. Real-Time Systems, 5(4):319--343, October

....actions that execute in the system. Although there are techniques to measure or calculate these execution times [9] 10] this is always a difficult task because of the unpredictability of the different execution paths within the program. Today s computer architectures with superscalar processors [11] and caches [8] make the prediction of execution times even more difficult, specially in the context of concurrent programs in which cache misses are frequent after interrupt service routines or context switches. If the worst case execution time is underestimated, severe timing errors may occur, ....

N. Zhang, A. Burns, and M. Nicholson. "Pipelined Processors and Worst-Case Execution Times". Real-Time Systems Journal, Vol. 5, No. 1, pp. 31-62, 1993.

.... to be dealt with to achieve static WCET analysis: characterizing the possible execution paths, and computing the execution time of a given execution path in an accurate and safe manner by considering the hardware state (hardware level WCET analysis) Studied architectural features are pipelines [16, 7], caches [10] and branch prediction [3] The most common focus for static WCET analysis is user code. Moreover, most published results on static WCET analysis (except [6] have been experimented on small scientific benchmark programs. The study described in [6] copes with more complex programs; ....

N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. Real-Time Systems, 5(4):319--343, Oct. 1993.

.... on WCET analysis introduced extensions of high level programming languages to describe possible execution paths [Kligerman, Stoyenko 1986, Puschner, Koza 1989, Park 1993] constructed tools for machine level WCET analysis [Mok, Amerasinghe et al. 1989, Park, Shaw 1990, Harmon, Baker, Whalley 1992, Zhang, Burns, Nicholson 1993, Li, Malik, Wolfe 1995] and they built compiler prototypes to translate high level source programs annotated with path information into code that is both executable and analyzable with respect to its WCET [Stoyenko 1987, Vrchoticky 1994] Despite the existence of the necessary research results ....

N. Zhang, A. Burns, and M. Nicholson. Pipelined Processors and Worst Case Execution Times. Real-Time Systems, 5(4):319--343, Oct. 1993.

....a number of research groups have addressed various issues in the area of predicting the WCET of real time programs. Conventional methods for static analysis have been extended from unoptimized programs on simple CISC processors [28, 26, 10, 27] to optimized programs on pipelined RISC processors [33, 19, 13], and from uncached architectures to instruction caches [4, 17, 15] and data caches [29, 16, 18] The possibility of an extension of Park s timing schema for set associative caches is brie y mentioned in [19] Li et al. 18] have described a framework to integrate caching into their integer ....

N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. Real-Time Systems, 5(4):319-343, October 1993.

.... to be dealt with to achieve WCET analysis: characterizing the possible execution paths, and computing the execution time of a given execution path in an accurate and safe manner by considering the hardware state (hardware level execution time analysis) Studied architectural features are pipelines [17, 7], caches [9, 10] and branch prediction [4] Most published results on WCET analysis were experimented on small benchmark programs. We are not aware of any use of WCET analysis on the code of large applications (except [5] which is described below) In particular, to our knowledge, no prior study ....

N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. Real-Time Systems, 5(4):319--343, October 1993. PI n1277

....microarchitecture, Heptane takes into account the effect of instruction cache, pipeline and branch prediction when computing programs wcets. Pipeline. The presence of pipelines is considered by simulating the flow of instructions in the pipelines, in a method similar to the one proposed in [1]. Instruction cache. Consideration of instruction cache uses static cache simulation [2] every instruction is classified according to its worst case behavior with respect to the instruction cache. The instruction classification process uses both the program syntax tree and control flow graph. ....

N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. Real-Time Systems, 5(4):319--343, October 1993.

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N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. Journal of Real-Time Systems, 5:319--343, October

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N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. Journal of Real-Time Systems, 5:319--343, October 1993.

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N. Zhang, A. Burns and M. Nicholson, "Pipelined Processors and Worst Case Execution Times", The Journal of Real-Time Systems 5, pp. 319-343, Department of Computer Science, University of York (1993).

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N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. Real-Time Systems, 5(4):319--343, Oct. 1993.

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N. Zhang, A. Burns, and M. Nicholson. Pipelined Processors and Worst-Case Execution Times. Real-Time Systems, 5(4):319--343, Oct. 1993.

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N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. Real-Time Systems, 5(4):319--343, Oct. 1993.

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N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. Real-Time Systems, 5(4):319-343, Oct. 1993.

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N. Zhang, A. Burns, and M. Nicholson. Pipelined Processors and Worst Case Execution Times. Journal of Real-Time Systems, 5(4):319--343, 1993. 10

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N. Zhang, A. Burns, and M. Nicholson, "Pipelined processors and worst case execution times," J. Real-Time Syst., vol. 5, pp. 319--343, Oct. 1993.

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N. Zhang, A, Bruns, M. Nicholson, Pipelined Processors and Worst Case Execution Times, The Journal of Real--Time Systems, 5, 319--343 (1993). 18

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