Q. Yang, "Introducing a New Cache Design into Vector Computers", IEEE Trans. on Computers, vol. 42, no. 12, pp. 1411-1424, 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....vector computers, the memory hierarchy had a big number of registers in the lowest level and a main memory organized in modules. In the current systems, a cache memory level for scalar data has been widely used, and the use of the cache level for vector data is the subject of nowadays research [1, 2]. The main memory is organized into a set of independent modules that can be accessed in parallel with the aim of increasing bandwidth and throughput. This organization in modules is typical not only in vector processors but it is also quite common in any high performance system. In uniprocessor ....

Q. Yang, "Introducing a New Cache Design into Vector Computers", IEEE Trans. on Computers, vol. 42, no. 12, pp. 1411-1424, 1993.

....such as permutations or rakes. The main benefits of a vector data cache arise from capturing temporal locality. Reusing vector data from cache reduces data bandwidth demands on the lower levels of the memory hierarchy. Large capacity and high associativity, or other techniques to avoid conflicts [Yan93] help to capture temporal locality. Vector data caches can also improve performance by reducing memory latency, though this is less important than in scalar processors due to the inherent latency tolerance of vector instructions. In particular, speculative prefetching to reduce latency may be ....

Q. Yang. Introducing a new cache design into vector computers. IEEE Transactions on Computers, 42(12):1411--1424, December 1993.

....results suggest a need to improve the memory performance in vector architectures. Unfortunately, typical hardware techniques used in scalar processors to improve memory usage and reduce memory latency have not always been useful in vector architectures. For example, data caches have been studied [16, 10, 33]; however, the results are mixed, with performance gain or loss depending on working set sizes and the fraction of non unit stride memory access. Data caches have not been put into widespread use in vector processors (except to cache scalar data) Dynamic instruction issue is used in scalar ....

Q. Yang. Introducing a new cache design into vector computers. IEEE Transactions on Computers, 52(12):1411--1424, Dec. 1993.

....the order of 4 16 slots) If load data were to be kept in the cache it would rapidly overflow its contents and negate any of the spill code elimination effects that we are seeking. This is the main difference of this proposal with respect to previous cache proposal for vector processors, such as [10, 13, 8, 7]. We term this cache as a victim cache because it only keeps data that has been evicted from the register file through a store instruction. In this sense, our cache follows the same spirit as the victim caches proposed and studied in [9] The main differences with other approaches is that our ....

....Perfect Club programs and report that results are very much dependent on stride patterns. Gee and Smith [8] also studied the general problem of caching using traces from a Cray X MP and the Ardent Titan, but focused on caching all types of references. Following the general caching technique, Yang [13] presented the primemapped cache for vector machines, which improved upon previous designs. Partial solutions specifically targeted at the spill problem where presented in two previous papers. In [4] the same idea of spill code elimination was implemented using the load store data queues present ....

Q. Yang. Introducing a new cache design into vector computers. IEEE Transactions on Computers, 52(12):1411--1424, December 1993.

....4 16 slots) If load data were to be kept in the cache it would rapidly overflow its contents and negate any of the spill code elimination effects that we are seeking. This is the main difference of this proposal with respect to previous cache proposal for vector processors, such as [KSF 94, Yan93, GS92, FP91b] A victim cache for vector registers 175 REG. FILE REG. FILE Write Through Write Back VICTIM VICTIM MEMORY MEMORY Figure 8.1 Write Through and Write back architectures. We term this cache as a victim cache because it only keeps data that has been evicted form the register file ....

....Club programs and report that results are very much dependent on stride patterns. Gee and Smith [GS92] also studied the general problem of caching using traces from a Cray X MP and the Ardent Titan, but focused on caching all types of references. Following the general caching technique, Yang [Yan93] presented the prime mapped cache for vector machines, which improved upon previous designs. Kontothanassis et al. KSF 94] compared the performance of a DRAM main memory systems against the traditional SRAM memory system and against different sizes of cache based DRAM memory systems. 8.9 ....

Qing Yang. Introducing a new cache design into vector computers. IEEE Transactions on Computers, 52(12):1411--1424, December 1993.

....researchers [5, 6, 7] but not yet been developed for CC NUMA memory management. The prime mapping scheme is based on the allocation of data pages to memories according to a prime number. The use of a prime number for effective distribution of data accesses has been studied in a few papers [8, 9]. Lawrie [8] described a memory system designed for parallel array access which based on the use of a prime number of memories in SIMD computers. Recently, Yang [9] presented a prime mapped cache in the vector processing environment. The memory access logic of the new allocation schemes is similar ....

....according to a prime number. The use of a prime number for effective distribution of data accesses has been studied in a few papers [8, 9] Lawrie [8] described a memory system designed for parallel array access which based on the use of a prime number of memories in SIMD computers. Recently, Yang [9] presented a prime mapped cache in the vector processing environment. The memory access logic of the new allocation schemes is similar to those of the existing policies, resulting in no additional delay for memory accesses. Our aim in this paper is to present these memory management techniques for ....

Q. Yang, "Introducing a New Cache Design into Vector Computers," IEEE Transations on Computers, vol. c-42, no. 12, pp. 1411-1424, Dec. 1993.

....between the data area and the tag area, that is, each cache line in the data area has one and only one address tag corresponding to it in the tag area. For good cache performance, we would like to have a large data area, since the cache hit ratio increases with the increase of cache size [7] 8] [9]. However, increasing data area also results in an increase in the tag area. Such an increase in the tag area will be magnified in the future as technology advances. Fig. 1 shows the ratios of tag area to data area in a 16K byte cache, with two different cache line sizes (16 bytes and 64 bytes) ....

Q. Yang, "Introducing a New Cache Design into Vector Computers, " IEEE Trans. Computers, vol. 43, no. 1, pp. , Jan. 1994.

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Q. Yang, "Introducing a New Cache Design into Vector Computers", IEEE Trans. on Computers, vol. 42, no. 12, pp. 1411-1424, 1993.

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