K. Julsgaard and Z. Xu, A VLSI implementation of the MAXLIST algorithm. Project report for CS/EE 542, University of Utah, 1995. Home/Search Document Not in Database Summary Related Articles Check |
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Specification And Compilation Of Timed Systems - Zheng (1998) (11 citations) (Correct)
....maximum delays also improve to 18.9 and 122.2 gate delays, respectively. 4.2.5 Comparison We compared our results with several synchronous implementations of the MAXLIST algorithm that were designed as class projects at the University of Utah. The best implementation designed by Julsgaard and Xu [13] had a clock frequency of 75 MHz for a 1:2 m CMOS process, and it required 6 2X cycles to accept a new datum and output the current maximum where X is the number of comparisons required. On average, they need 1.4 comparisons, or 117ns. Assuming a 0:5ns gate delay for this process, this 0 20 40 60 ....
K. Julsgaard and Z. Xu, A VLSI implementation of the MAXLIST algorithm. Project report for CS/EE 542, University of Utah, 1995.
An Asynchronous Implementation Of The Maxlist Algorithm - Chris Myers (1997) (Correct)
....maximum delays also improve to 19.1 and 124.3 gate delays, respectively. 6. COMPARISON We compared our results with several synchronous implementations of the MAXLIST algorithm that were designed as class projects at the University of Utah. The best implementation designed by Julsgaard and Xu [6] had a clock frequency of 75 MHz for a 1:2 m CMOS process, and it required 6 2X cycles to accept a new datum and output the current maximum where X is the number of comparisons required. On average, they need 1.4 comparisons, or 117ns. Assuming a 0:5ns gate delay for this process, this ....
K. Julsgaard and Z. Xu. A VLSI implementation of the MAXLIST algorithm. Project report for CS/EE 542,
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